From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 787FF22156A for ; Thu, 27 Nov 2025 14:17:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764253062; cv=none; b=CSQFn2/xJUgzTbESuzd5LXJgBWReflve4HTUjcSnNeXaTNqWFtKZUA5ij3ehFX+omjnUGbCHkwZLbm4v7bEPntVodjLKsIumb/J1yePuTZVp63HECRpVJOm8eBbK5ax0uq/Ki2M3FmmC3RF3Hhoi7m6IPPT1L/jDrf9IUwqlwTc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764253062; c=relaxed/simple; bh=4haNjzaDLe2vliXcpa8qTI93RvKyr77GcBCX063zobE=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=e/kBFn177ZOLe9AI+n5r6RiKQp8G1Qq7yiGCRJfI/lJr6eAKln5+1YloNYYCV26xWFMkHTnfTaF+TimDzamKq8GY6VMV4RArTlPTOgCd3+ZioLLIHEQlEAUVCYXBa4nps1MkRUWFvdb0AiIe13AYmYUKGq1VgSBPJ+VkIc77ciU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oJfLpIm4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oJfLpIm4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F196FC4CEF8; Thu, 27 Nov 2025 14:17:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764253062; bh=4haNjzaDLe2vliXcpa8qTI93RvKyr77GcBCX063zobE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=oJfLpIm4JlHsksbmJy0cXlKOUMYyE+upDpGy8s/Yxp78yH/zDUiXw1zKUm0+1SDu7 2bcPrY1W16tK823RM9U096AsMWLrmfnr9Lz1cmNQF2RHRITB0zxiRlRkDQKtKbeV+k MG6OfKL91j5bM52CRWQ4+l8BDO2h5zud3IVF499gmnk09IamtmN0bENxMZ+Jl2KbBZ GPh3gCPIc+MwEMN5VeO+PAsv2mZ5KS4GSUicg0yJ5GGnM6Gw/so2UuwJuevetpN5C4 3x2YNEQKQ05O5qaPayjH+e5phAhEqBWPyaWpPCIz7Bm4hbJrTRLGrCe32P60bSjK6u /PcJVfxwAvA0g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vOcoV-00000008oYy-2CpF; Thu, 27 Nov 2025 14:17:39 +0000 Date: Thu, 27 Nov 2025 14:17:39 +0000 Message-ID: <86345zr24c.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org Subject: Re: [PATCH v1 4/5] arm64: Inject UNDEF when accessing MTE sysregs with MTE disabled In-Reply-To: <20251127122210.4111702-5-tabba@google.com> References: <20251127122210.4111702-1-tabba@google.com> <20251127122210.4111702-5-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 27 Nov 2025 12:22:09 +0000, Fuad Tabba wrote: > > When MTE hardware is present but disabled via software (arm64.nomte or > CONFIG_ARM64_MTE=n), HCR_EL2.ATA is cleared to prevent use of MTE > instructions. However, this alone doesn't fully emulate hardware that > lacks MTE support. > > With HCR_EL2.ATA cleared, accesses to certain MTE system registers trap > to EL2 with exception class ESR_ELx_EC_SYS64. To faithfully emulate > hardware without MTE (where such accesses would cause an Undefined > Instruction exception), inject UNDEF into the host. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 44 ++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > index 29430c031095..f542e4c17156 100644 > --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c > @@ -686,6 +686,46 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt) > kvm_skip_host_instr(); > } > > +static void inject_undef64(void) > +{ > + unsigned long sctlr, vbar, old, new; > + u64 offset, esr; > + > + vbar = read_sysreg_el1(SYS_VBAR); > + sctlr = read_sysreg_el1(SYS_SCTLR); > + old = read_sysreg_el2(SYS_SPSR); > + new = get_except64_cpsr(old, system_supports_mte(), sctlr, PSR_MODE_EL1h); > + offset = get_except64_offset(old, PSR_MODE_EL1h, except_type_sync); > + esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT) | ESR_ELx_IL; > + > + write_sysreg_el1(esr, SYS_ESR); > + write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR); > + write_sysreg_el1(old, SYS_SPSR); > + write_sysreg_el2(vbar + offset, SYS_ELR); > + write_sysreg_el2(new, SYS_SPSR); > +} > + > +static bool handle_host_mte(u64 esr) > +{ > + /* If we're here for any reason other than MTE, then it's a bug. */ > + > + if (read_sysreg(HCR_EL2) & HCR_ATA) > + return false; > + > + switch (esr_sys64_to_sysreg(esr)) { > + case SYS_RGSR_EL1: > + case SYS_GCR_EL1: > + case SYS_TFSR_EL1: > + case SYS_TFSRE0_EL1: How about other things, such as DC GVA? Don't you need to trap and UNDEF it (which has the side effect of also trapping DC ZVA)? Same question for all the DC {C,I,CI}GVA{C,P} instructions. Thanks, M. -- Without deviation from the norm, progress is not possible.