Re: [PATCH 01/10] arm64: sysreg: Add new PMSIDR_EL1 and PMSFCR_EL1 fields

[Marc Zyngier <maz@kernel.org>]

On Tue, 06 May 2025 12:41:33 +0100,
James Clark <james.clark@linaro.org> wrote:
> 
> Add new fields and registers that are introduced for the features
> FEAT_SPE_CRR (call return records), FEAT_SPE_EFT (extended filtering),
> FEAT_SPE_FPF (floating point flag), FEAT_SPE_FDS (data source
> filtering), FEAT_SPE_ALTCLK and FEAT_SPE_SME.
>
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
>  arch/arm64/tools/sysreg | 26 ++++++++++++++++++++++----
>  1 file changed, 22 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index bdf044c5d11b..80d57c83a5f5 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -2205,11 +2205,20 @@ Field	0	RND
>  EndSysreg
>  
>  Sysreg	PMSFCR_EL1	3	0	9	9	4
> -Res0	63:19
> +Res0	63:53
> +Field	52	SIMDm
> +Field	51	FPm
> +Field	50	STm
> +Field	49	LDm
> +Field	48	Bm
> +Res0	47:21
> +Field	20	SIMD
> +Field	19	FP
>  Field	18	ST
>  Field	17	LD
>  Field	16	B
> -Res0	15:4
> +Res0	15:5
> +Field	4	FDS
>  Field	3	FnE
>  Field	2	FL
>  Field	1	FT
> @@ -2226,7 +2235,12 @@ Field	15:0	MINLAT
>  EndSysreg
>  
>  Sysreg	PMSIDR_EL1	3	0	9	9	7
> -Res0	63:25
> +Res0	63:33
> +Field	32	SME
> +Field	31:28	ALTCLK
> +Field	27	FPF
> +Field	26	EFT
> +Field	25	CRR

These are described as enumerations in the JSON file (see [1]).

	M.

[1] https://lore.kernel.org/all/20250506164348.346001-7-maz@kernel.org

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