From: Marc Zyngier <maz@kernel.org>
To: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Joey Gouly <joey.gouly@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Przemyslaw Gaj <pgaj@cadence.com>
Subject: Re: [PATCH v2 13/17] KVM: arm64: nv: Add SW walker for AT S1 emulation
Date: Mon, 12 Aug 2024 18:58:24 +0100 [thread overview]
Message-ID: <8634n91v3z.wl-maz@kernel.org> (raw)
In-Reply-To: <ZromBtfbjaHbcjT7@arm.com>
Hi Alex,
On Mon, 12 Aug 2024 16:11:02 +0100,
Alexandru Elisei <alexandru.elisei@arm.com> wrote:
>
> Hi Marc,
>
> On Sat, Aug 10, 2024 at 11:16:15AM +0100, Marc Zyngier wrote:
> > Hi Alex,
> >
> > @@ -136,12 +137,22 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi,
> > va = (u64)sign_extend64(va, 55);
> >
> > /* Let's put the MMU disabled case aside immediately */
> > - if (!(sctlr & SCTLR_ELx_M) ||
> > - (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)) {
> > + switch (wi->regime) {
> > + case TR_EL10:
> > + if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)
> > + wr->level = S1_MMU_DISABLED;
>
> In compute_translation_regime(), for AT instructions other than AT S1E2*, when
> {E2H,TGE} = {0,1}, regime is Regime_EL10. As far as I can tell, when regime is
> Regime_EL10 and TGE is set, stage 1 is disabled, according to
> AArch64.S1Enabled() and the decription of the TGE bit.
Grmbl... I really dislike E2H=0. May it die a painful death. How about
this on top?
diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index 10017d990bc3..870e77266f80 100644
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -139,7 +139,19 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi,
/* Let's put the MMU disabled case aside immediately */
switch (wi->regime) {
case TR_EL10:
- if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)
+ /*
+ * If dealing with the EL1&0 translation regime, 3 things
+ * can disable the S1 translation:
+ *
+ * - HCR_EL2.DC = 0
+ * - HCR_EL2.{E2H,TGE} = {0,1}
+ * - SCTLR_EL1.M = 0
+ *
+ * The TGE part is interesting. If we have decided that this
+ * is EL1&0, then it means that either {E2H,TGE} == {1,0} or
+ * {0,x}, and we only need to test for TGE == 1.
+ */
+ if (__vcpu_sys_reg(vcpu, HCR_EL2) & (HCR_DC | HCR_TGE))
wr->level = S1_MMU_DISABLED;
fallthrough;
case TR_EL2:
[...]
>
> switch (desc & GENMASK_ULL(1, 0)) {
> case 0b00:
> case 0b10:
> goto transfault;
> case 0b01:
> /* Block mapping */
> break;
> default:
> if (level == 3)
> break;
> }
>
> Is this better? Perhaps slightly easier to match against the descriptor layouts,
> but I'm not sure it's an improvement over your suggestion. Up to you, no point
> in bikeshedding over it.
I think I'll leave it as is for now. I'm getting sick of this code...
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2024-08-12 17:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-31 19:40 [PATCH v2 00/17] KVM: arm64: nv: Add support for address translation instructions Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 01/17] arm64: Add missing APTable and TCR_ELx.HPD masks Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 02/17] arm64: Add PAR_EL1 field description Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 03/17] arm64: Add system register encoding for PSTATE.PAN Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 04/17] arm64: Add ESR_ELx_FSC_ADDRSZ_L() helper Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 05/17] KVM: arm64: Make kvm_at() take an OP_AT_* Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 06/17] KVM: arm64: nv: Turn upper_attr for S2 walk into the full descriptor Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 07/17] KVM: arm64: nv: Honor absence of FEAT_PAN2 Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 08/17] KVM: arm64: nv: Add basic emulation of AT S1E{0,1}{R,W} Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 09/17] KVM: arm64: nv: Add basic emulation of AT S1E1{R,W}P Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 10/17] KVM: arm64: nv: Add basic emulation of AT S1E2{R,W} Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 11/17] KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W} Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 12/17] KVM: arm64: nv: Make ps_to_output_size() generally available Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 13/17] KVM: arm64: nv: Add SW walker for AT S1 emulation Marc Zyngier
2024-08-09 12:43 ` Alexandru Elisei
2024-08-10 10:16 ` Marc Zyngier
2024-08-12 15:11 ` Alexandru Elisei
2024-08-12 17:58 ` Marc Zyngier [this message]
2024-08-12 18:04 ` Marc Zyngier
2024-08-13 9:17 ` Alexandru Elisei
2024-07-31 19:40 ` [PATCH v2 14/17] KVM: arm64: nv: Sanitise SCTLR_EL1.EPAN according to VM configuration Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 15/17] KVM: arm64: nv: Make AT+PAN instructions aware of FEAT_PAN3 Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 16/17] KVM: arm64: nv: Plumb handling of AT S1* traps from EL2 Marc Zyngier
2024-07-31 19:40 ` [PATCH v2 17/17] KVM: arm64: nv: Add support for FEAT_ATS1A Marc Zyngier
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