From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A96DBFBFD for ; Mon, 7 Aug 2023 19:00:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FF2DC433C7; Mon, 7 Aug 2023 19:00:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1691434816; bh=5m/STA9PtNQsOcqTfXz0N1bOmLM90be5DraJdYGbRX4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=aOC3wppc54KI8adDp8a0TfI+Ua3xrybFZ7ENmAnEPnSFWRdS270ST/9Iy0bhDJ0GQ dx8gC86tIg3b5yL59IZCjyXTafgwgzsVw8HPW5k3ks/ldxlcMeH2EBTnSFMlNsxowo 5rH8VzVOSgyarSD1KEAqa8nOL8xteML3/v831i/U4K7MARff2ikE/NRadQSfYToPmU x0nLfpd9f4BkUJciflDdQD8FEeh+D+Uco1CM1tIPoWy6iiTTDS+NqczGuhXf6hVHOn Kn9Ww2UscOPdiTU50DDxw1J/Ou6Pw3IemgTso1Tzi2L2aEo+8Wr4WEVjGaZqwZlqEf 20JiDIqxqnp6A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qT5Sf-002vSP-M7; Mon, 07 Aug 2023 20:00:13 +0100 Date: Mon, 07 Aug 2023 20:00:12 +0100 Message-ID: <867cq665kz.wl-maz@kernel.org> From: Marc Zyngier To: eric.auger@redhat.com Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Mark Brown , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , Miguel Luis , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH v2 21/26] KVM: arm64: nv: Add trap forwarding for HDFGxTR_EL2 In-Reply-To: References: <20230728082952.959212-1-maz@kernel.org> <20230728082952.959212-22-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: eric.auger@redhat.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, broonie@kernel.org, mark.rutland@arm.com, will@kernel.org, alexandru.elisei@arm.com, andre.przywara@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com, darren@os.amperecomputing.com, miguel.luis@oracle.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Hi Eric, On Mon, 07 Aug 2023 18:19:16 +0100, Eric Auger wrote: > > Hi Marc, > On 7/28/23 10:29, Marc Zyngier wrote: > > ... and finally, the Debug version of FGT, with its *enormous* > > list of trapped registers. > > > > Reviewed-by: Suzuki K Poulose > > Reviewed-by: Eric Auger > Hi Marc, I think you mixed up with the R-b's sent on > [PATCH v2 06/26] arm64: Add debug registers affected by HDFGxTR_EL2 Most probably. Really sorry about that. I'll fix that right away. > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_arm.h | 11 + > > arch/arm64/kvm/emulate-nested.c | 460 +++++++++++++++++++++++++++++++ [...] > > + SR_FGT(SYS_TRCIMSPEC0, HDFGRTR, TRCIMSPECn, 1), > why not SYS_TRCIMSPEC(0)? Yup, it's been mentioned a couple of time already, now fixed. > > + SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1), > > + SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1), > what about all of the TRCIDR regs refered to in the spec? Ah, nothing escapes you! Yup totally missed it, now added. [...] > > + SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1),y > > + SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1),y > > + SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1), > nit: maybe put this one before the > > SYS_TRCRSCTLR(n) series to follow the spec order Done. [...] > > + /* > > + * HDFGWTR_EL2 > > + * > > + * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely > > + * overlap in their bit assignment, there are a number of bits > > + * that are RES0 on one side, and an actual trap bit on the > > + * other. The policy chosen here is to describe all the > > + * read-side mappings, and only the write-side mappings that > > + * differ from the write side, and the trap handler will pick > differ from the read side? Well spotted! Now fixed. Thanks again! M. -- Without deviation from the norm, progress is not possible. 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b=aOC3wppc54KI8adDp8a0TfI+Ua3xrybFZ7ENmAnEPnSFWRdS270ST/9Iy0bhDJ0GQ dx8gC86tIg3b5yL59IZCjyXTafgwgzsVw8HPW5k3ks/ldxlcMeH2EBTnSFMlNsxowo 5rH8VzVOSgyarSD1KEAqa8nOL8xteML3/v831i/U4K7MARff2ikE/NRadQSfYToPmU x0nLfpd9f4BkUJciflDdQD8FEeh+D+Uco1CM1tIPoWy6iiTTDS+NqczGuhXf6hVHOn Kn9Ww2UscOPdiTU50DDxw1J/Ou6Pw3IemgTso1Tzi2L2aEo+8Wr4WEVjGaZqwZlqEf 20JiDIqxqnp6A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qT5Sf-002vSP-M7; Mon, 07 Aug 2023 20:00:13 +0100 Date: Mon, 07 Aug 2023 20:00:12 +0100 Message-ID: <867cq665kz.wl-maz@kernel.org> From: Marc Zyngier To: eric.auger@redhat.com Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Mark Brown , Mark Rutland , Will Deacon , Alexandru Elisei , Andre Przywara , Chase Conklin , Ganapatrao Kulkarni , Darren Hart , Miguel Luis , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH v2 21/26] KVM: arm64: nv: Add trap forwarding for HDFGxTR_EL2 In-Reply-To: References: <20230728082952.959212-1-maz@kernel.org> <20230728082952.959212-22-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: eric.auger@redhat.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, broonie@kernel.org, mark.rutland@arm.com, will@kernel.org, alexandru.elisei@arm.com, andre.przywara@arm.com, chase.conklin@arm.com, gankulkarni@os.amperecomputing.com, darren@os.amperecomputing.com, miguel.luis@oracle.com, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230807_120017_703513_9EE63665 X-CRM114-Status: GOOD ( 24.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Eric, On Mon, 07 Aug 2023 18:19:16 +0100, Eric Auger wrote: > > Hi Marc, > On 7/28/23 10:29, Marc Zyngier wrote: > > ... and finally, the Debug version of FGT, with its *enormous* > > list of trapped registers. > > > > Reviewed-by: Suzuki K Poulose > > Reviewed-by: Eric Auger > Hi Marc, I think you mixed up with the R-b's sent on > [PATCH v2 06/26] arm64: Add debug registers affected by HDFGxTR_EL2 Most probably. Really sorry about that. I'll fix that right away. > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_arm.h | 11 + > > arch/arm64/kvm/emulate-nested.c | 460 +++++++++++++++++++++++++++++++ [...] > > + SR_FGT(SYS_TRCIMSPEC0, HDFGRTR, TRCIMSPECn, 1), > why not SYS_TRCIMSPEC(0)? Yup, it's been mentioned a couple of time already, now fixed. > > + SR_FGT(SYS_TRCIMSPEC(1), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(2), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(3), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(4), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(5), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(6), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCIMSPEC(7), HDFGRTR, TRCIMSPECn, 1), > > + SR_FGT(SYS_TRCDEVARCH, HDFGRTR, TRCID, 1), > > + SR_FGT(SYS_TRCDEVID, HDFGRTR, TRCID, 1), > what about all of the TRCIDR regs refered to in the spec? Ah, nothing escapes you! Yup totally missed it, now added. [...] > > + SR_FGT(SYS_TRCRSCTLR(2), HDFGRTR, TRC, 1),y > > + SR_FGT(SYS_TRCRSCTLR(3), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(4), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(5), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(6), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(7), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(8), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(9), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(10), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(11), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(12), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(13), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(14), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(15), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(16), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(17), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(18), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(19), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(20), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(21), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(22), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(23), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(24), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(25), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(26), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(27), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(28), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(29), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(30), HDFGRTR, TRC, 1), > > + SR_FGT(SYS_TRCRSCTLR(31), HDFGRTR, TRC, 1),y > > + SR_FGT(SYS_TRCQCTLR, HDFGRTR, TRC, 1), > nit: maybe put this one before the > > SYS_TRCRSCTLR(n) series to follow the spec order Done. [...] > > + /* > > + * HDFGWTR_EL2 > > + * > > + * Although HDFGRTR_EL2 and HDFGWTR_EL2 registers largely > > + * overlap in their bit assignment, there are a number of bits > > + * that are RES0 on one side, and an actual trap bit on the > > + * other. The policy chosen here is to describe all the > > + * read-side mappings, and only the write-side mappings that > > + * differ from the write side, and the trap handler will pick > differ from the read side? Well spotted! Now fixed. Thanks again! M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel