From: Marc Zyngier <maz@kernel.org>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
nd <nd@arm.com>, "lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"tglx@kernel.org" <tglx@kernel.org>,
Catalin Marinas <Catalin.Marinas@arm.com>,
"will@kernel.org" <will@kernel.org>,
Mark Rutland <Mark.Rutland@arm.com>,
Sashiko <sashiko-bot@kernel.org>
Subject: Re: [PATCH v2] irqchip/gic-v5: Preserve ICC_CR0_EL1 state
Date: Mon, 07 Sep 2026 18:50:14 +0100 [thread overview]
Message-ID: <868q5d3q95.wl-maz@kernel.org> (raw)
In-Reply-To: <20260907164945.714545-1-sascha.bischoff@arm.com>
On Mon, 07 Sep 2026 17:49:50 +0100,
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
>
> In addition to EN, ICC_CR0_EL1 contains other fields, such as LINK and
> LINK_IDLE. The driver only needs to modify EN, and must preserve the
> values of all other fields when enabling or disabling the CPU
> interface.
>
> Define the missing LINK and LINK_IDLE fields, and use read-modify-write
> accesses to update EN without affecting the rest of ICC_CR0_EL1.
>
> Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support")
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Closes: https://lore.kernel.org/r/20260807121703.D4B7A1F00A3A@smtp.kernel.org
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
prev parent reply other threads:[~2026-09-07 17:50 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 16:49 [PATCH v2] irqchip/gic-v5: Preserve ICC_CR0_EL1 state Sascha Bischoff
2026-09-07 17:50 ` Marc Zyngier [this message]
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