From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6824843634E; Fri, 15 May 2026 09:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778836711; cv=none; b=CoOearM1gCXlYRHoEBcT8HTuaP9+LFJSW27FIDn/cKGc2SUTnKjZz8QBp0MXvMmMUeKxkWnecF2iFAR3Vd21OHEzdIug2tXZkkiHxKcLO6Yy/HdxY6iRf9ghUEP6uHKGrfBPYZ89264NLom2KlBrkIoN+GR3CMBqO1nDWLfZ5nE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778836711; c=relaxed/simple; bh=sYJkxXH6j8B1Q6LjHly6ZYrPdda51JI2AeI8/2x3VYM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=GnjvxdYHB04+tJrulGDIPoQZIQQ3oFnCwnktcyORs4coLHKpgc6iU87VI4x7RKq+5WluyCnDBAUZCWRFBAHRKBLPVyiTOowQQR9tgnF0jRV3GddK/MDyqc/ICKPMfyGbajcojYGiKobNyi38a0FQ5soO4W4t8/wX8OE21uaDRmw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OYrXmIZL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OYrXmIZL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F3ED7C2BCB0; Fri, 15 May 2026 09:18:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778836711; bh=sYJkxXH6j8B1Q6LjHly6ZYrPdda51JI2AeI8/2x3VYM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OYrXmIZLtCErLj9FpTh1lflLun7XYQYh63YeyBlrt639I5hkV07S6BaVRdmdCz8Vy mplI28eWqxOu84QyykKFQhiMCZh8v+yl7uWZvF5k5CByXbv5mdQj+/eaeU5c6Vcmrh a9u8+0AEeWmbzhV1flOQUYEbxjWuL7iYsDP3QCAjNwj3An0XAIZmDyPazmOKYhE8PF Nzw8k570vgm8b95LQKWeDyD0T+Qm70AuUPjPF7EO3GW93IijPRBbXBz/uyS4zKfCwl AZMS/trYRtqztD+TRjvxnsCeMRVy3wfewf1zUkQQlOF3ETJF3DmGTdOI/wv1iGBVVc QNMqghOiWGJvQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wNoge-00000002dBv-3yZ6; Fri, 15 May 2026 09:18:29 +0000 Date: Fri, 15 May 2026 10:18:28 +0100 Message-ID: <868q9lxc7v.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: robh@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org Subject: Re: [PATCH v2 04/17] dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description In-Reply-To: <20260514213713.5D47FC2BCB3@smtp.kernel.org> References: <20260514150945.3917510-5-maz@kernel.org> <20260514213713.5D47FC2BCB3@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, robh@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 14 May 2026 22:37:07 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: > - [Critical] The schema permits omitting the EL3 secure timer but fails to make `interrupt-names` a required property, which allows configurations that fatally misroute interrupts and hang the system. > - [Medium] The static `items` array with `minItems: 2` structurally fails to enforce the stated architectural rules and causes positional misalignment for valid configurations. > - [Medium] The commit incorrectly asserts that the EL1 virtual timer IRQ is 'always required', which misrepresents ARMv7 hardware and contradicts existing device trees. > -- > > commit 01733bbba71a7bef01e5c0820740d8ab21f684f8 > Author: Marc Zyngier > > dt-bindings: timer: arm,arch_timer: Fix requirements for interrupt description > > This commit updates the arm,arch_timer binding to clarify the requirements > for timer interrupts based on the implemented architecture. It raises the > minimum number of interrupts to two and uses architectural terminology. > > > Follow the architecture by making it explicit that: > > - the EL1 secure timer irq is required if EL3 is implemented > > - the EL1 physical timer irq is always required > > - the EL1 virtual timer irq is always required > > Is this description architecturally accurate for ARMv7? > > In ARMv7, Virtualization Extensions are optional, so hardware lacking these > extensions does not implement a virtual timer. Existing device trees, such > as arch/arm/boot/dts/rockchip/rv1108.dtsi, accurately reflect this by > providing exactly two physical interrupts (secure and non-secure) and > completely omitting the virtual timer. This *is* valid for all known implementations of ARMv7, as the architected timer is present only on implementations that have the virtualisation extensions. > Establishing the EL1 virtual timer as always required seems to contradict > these valid hardware configurations. That's because that DT was broken the first place. > > > diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > > --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > > +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml > > [ ... ] > > > @@ -33,13 +28,13 @@ properties: > > - const: arm,armv7-timer > > > > interrupts: > > - minItems: 1 > > + minItems: 2 > > items: > > - - description: secure timer irq > > - - description: non-secure timer irq > > - - description: virtual timer irq > > - - description: hypervisor timer irq > > - - description: hypervisor virtual timer irq > > + - description: EL1 secure physical timer irq, if EL3 is implemented > > + - description: EL1 non-secure physical timer irq > > + - description: EL1 virtual timer irq > > Will this static array structure cause positional misalignment and fail to > enforce the stated requirements? It always has been a problem, and this is worked around on the sole platform affected by this (APM XGene) by having a dummy interrupt for the secure timer. We could add a separate requirement that interrupt names must be provided if secure is not implemented, but I have no idea how to specify this. M. -- Without deviation from the norm, progress is not possible.