From: Marc Zyngier <maz@kernel.org>
To: Peter Chen <peter.chen@cixtech.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com,
marcin@juszkiewicz.com.pl,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Fugang Duan <fugang.duan@cixtech.com>
Subject: Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support
Date: Fri, 21 Mar 2025 11:01:47 +0000 [thread overview]
Message-ID: <868qoymyuc.wl-maz@kernel.org> (raw)
In-Reply-To: <Z91AG0lH1JNN7NHq@nchen-desktop>
On Fri, 21 Mar 2025 10:31:55 +0000,
Peter Chen <peter.chen@cixtech.com> wrote:
>
> On 25-03-21 09:04:00, Marc Zyngier wrote:
> > > On 25-03-20 09:36:37, Marc Zyngier wrote:
> > > > Peter Chen <peter.chen@cixtech.com> wrote:
> > > > >
> > > > > + pmu-a520 {
> > > > > + compatible = "arm,cortex-a520-pmu";
> > > > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> > > > > + };
> > > > > +
> > > > > + pmu-a720 {
> > > > > + compatible = "arm,cortex-a720-pmu";
> > > > > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> > > > > + };
> > > > > +
> > > > > + pmu-spe {
> > > > > + compatible = "arm,statistical-profiling-extension-v1";
> > > > > + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> > > > > + };
> > > >
> > > > SPE should follow the same model as the PMU, as each CPU has its own
> > > > SPE implementation, exposing different micro-architectural details.
> > > >
> > >
> > > Hi Marc,
> > >
> > > Thanks for your reply. But there is only one compatible string
> > > "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c,
> > > how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need
> > > to change arm_spe_pmu.c as well?
> >
> > I don't think there is a need to have different compatible. The driver
> > can probe which CPU this is on, and work out the implemented
> > subfeatures from the PMSIDR_EL1 register. New compatible strings are
> > better avoided when there is a way to probe/discover the HW (and in
> > most cases, there is).
> >
> > Note that this equally applies to TRBE, which also explicitly deals
> > with interrupt partitioning and yet only has a single compatible.
> > Please consider adding TRBE support when you repost this series.
> >
>
> Hi Marc,
>
> Thanks for your comment, we need to discuss it internally. Since it
> is very initial dts support for CIX sky1 SoC, I will delete pmu-spe
> support at this time, and add better support for it when adding
> more components next time.
And therefore making this machine even less useful than it already is?
<s> I think this is a great plan. </s>
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-03-21 11:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 5:38 [PATCH v4 0/6] arm64: Introduce CIX P1 (SKY1) SoC Peter Chen
2025-03-05 5:38 ` [PATCH v4 1/6] dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd Peter Chen
2025-03-05 5:38 ` [PATCH v4 2/6] dt-bindings: arm: add CIX P1 (SKY1) SoC Peter Chen
2025-03-05 5:38 ` [PATCH v4 3/6] arm64: Kconfig: add ARCH_CIX for cix silicons Peter Chen
2025-03-05 5:38 ` [PATCH v4 4/6] arm64: defconfig: Enable CIX SoC Peter Chen
2025-03-05 5:38 ` [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support Peter Chen
2025-03-20 9:36 ` Marc Zyngier
2025-03-20 9:57 ` Peter Chen
2025-03-21 9:04 ` Marc Zyngier
2025-03-21 10:31 ` Peter Chen
2025-03-21 11:01 ` Marc Zyngier [this message]
2025-03-05 5:38 ` [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry Peter Chen
2025-03-20 9:25 ` Krzysztof Kozlowski
2025-03-20 10:49 ` Peter Chen
2025-03-20 15:28 ` Kajetan Puchalski
2025-03-21 1:40 ` Peter Chen
2025-03-20 16:20 ` Krzysztof Kozlowski
2025-03-21 9:00 ` Arnd Bergmann
2025-03-11 1:02 ` [PATCH v4 0/6] arm64: Introduce CIX P1 (SKY1) SoC Peter Chen
2025-03-17 1:38 ` Peter Chen
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