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Sat, 15 Feb 2020 10:28:41 +0000 Date: Sat, 15 Feb 2020 10:28:39 +0000 Message-ID: <868sl46t60.wl-maz@kernel.org> From: Marc Zyngier To: Robin Murphy Subject: Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure In-Reply-To: References: <20200214183615.25498-1-maz@kernel.org> <20200214183615.25498-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Fri, 14 Feb 2020 22:01:01 +0000, Robin Murphy wrote: Hi Robin, > > Hi Marc, > > On 2020-02-14 6:36 pm, Marc Zyngier wrote: > [...] > > @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > > pmc->idx != ARMV8_PMU_CYCLE_IDX) > > return; > > + /* > > + * If we have a filter in place and that the event isn't allowed, do > > + * not install a perf event either. > > + */ > > + if (vcpu->kvm->arch.pmu_filter && > > + !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) > > + return; > > If I'm reading the derivation of eventsel right, this will end up > treating cycle counter events (aliased to SW_INCR) differently from > CPU_CYCLES, which doesn't seem desirable. Indeed, this doesn't look quite right. Looking at the description of event 0x11, it doesn't seem to count exactly like the cycle counter (there are a number of PMCR controls affecting it). But none of these actually apply to our PMU emulation (no secure mode, and the idea of dealing with virtual EL2 in the context of the PMU is... not appealing). Now, given that we implement the cycle counter with event 0x11 anyway, I don't think there is any reason to deal with them separately. > Also, if the user did try to blacklist SW_INCR for ridiculous > reasons, we'd need to special-case kvm_pmu_software_increment() to > make it (not) work as expected, right? I thought of that one, and couldn't see a reason to blacklist it (after all, the guest could also increment a variable) and send itself an interrupt. I'm tempted to simply document that event 0 is never filtered. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0781FC2BA83 for ; Sat, 15 Feb 2020 10:28:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C96512083B for ; Sat, 15 Feb 2020 10:28:55 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sat, 15 Feb 2020 10:28:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581762523; bh=bqNvuVUqkOIe/2rjy+xGqj4cWOzQabd8q++smLd+LlM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=y9lyvC8cZwBpKWuMdqpKDh91XEYIEb/PixpgJ2oScLmrucMBn6EHPTsDdPysWFm1U PlPTmtazVWMQvc3XxwDhybq579WvJkjXJeGKfM/qUwSiVsOwhDO+y2wtXUnIr7O3Cd 4SjJapaRDElBimzKRZLAFh1jAZdaJYm9J7WBy1Bg= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=big-swifty.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1j2ugj-005Qp1-P1; Sat, 15 Feb 2020 10:28:41 +0000 Date: Sat, 15 Feb 2020 10:28:39 +0000 Message-ID: <868sl46t60.wl-maz@kernel.org> From: Marc Zyngier To: Robin Murphy Subject: Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure In-Reply-To: References: <20200214183615.25498-1-maz@kernel.org> <20200214183615.25498-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200215_022844_215338_20ACABB7 X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Suzuki K Poulose , James Morse , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 14 Feb 2020 22:01:01 +0000, Robin Murphy wrote: Hi Robin, > > Hi Marc, > > On 2020-02-14 6:36 pm, Marc Zyngier wrote: > [...] > > @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > > pmc->idx != ARMV8_PMU_CYCLE_IDX) > > return; > > + /* > > + * If we have a filter in place and that the event isn't allowed, do > > + * not install a perf event either. > > + */ > > + if (vcpu->kvm->arch.pmu_filter && > > + !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) > > + return; > > If I'm reading the derivation of eventsel right, this will end up > treating cycle counter events (aliased to SW_INCR) differently from > CPU_CYCLES, which doesn't seem desirable. Indeed, this doesn't look quite right. Looking at the description of event 0x11, it doesn't seem to count exactly like the cycle counter (there are a number of PMCR controls affecting it). But none of these actually apply to our PMU emulation (no secure mode, and the idea of dealing with virtual EL2 in the context of the PMU is... not appealing). Now, given that we implement the cycle counter with event 0x11 anyway, I don't think there is any reason to deal with them separately. > Also, if the user did try to blacklist SW_INCR for ridiculous > reasons, we'd need to special-case kvm_pmu_software_increment() to > make it (not) work as expected, right? I thought of that one, and couldn't see a reason to blacklist it (after all, the guest could also increment a variable) and send itself an interrupt. I'm tempted to simply document that event 0 is never filtered. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A1C8C2BA83 for ; Sat, 15 Feb 2020 10:28:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5EB672084E for ; Sat, 15 Feb 2020 10:28:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581762525; bh=bqNvuVUqkOIe/2rjy+xGqj4cWOzQabd8q++smLd+LlM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=NjpdfVt2Hw/iXqo+Rc8PC6OxJeHszyldGwuB37/keYIadD0/ID3VCcanfDH12c5sC QaozfRbyS8kItcY3mpmx33R4EK58sloWQKBn1lchHS9OExsUnaemHh7lPqmkYsr31J FJ5GfC27800fzmcQvcGT07YJZfhb9MFgu0HQrUnU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725971AbgBOK2o (ORCPT ); Sat, 15 Feb 2020 05:28:44 -0500 Received: from mail.kernel.org ([198.145.29.99]:54656 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725937AbgBOK2o (ORCPT ); Sat, 15 Feb 2020 05:28:44 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8CF162083B; Sat, 15 Feb 2020 10:28:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581762523; bh=bqNvuVUqkOIe/2rjy+xGqj4cWOzQabd8q++smLd+LlM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=y9lyvC8cZwBpKWuMdqpKDh91XEYIEb/PixpgJ2oScLmrucMBn6EHPTsDdPysWFm1U PlPTmtazVWMQvc3XxwDhybq579WvJkjXJeGKfM/qUwSiVsOwhDO+y2wtXUnIr7O3Cd 4SjJapaRDElBimzKRZLAFh1jAZdaJYm9J7WBy1Bg= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=big-swifty.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1j2ugj-005Qp1-P1; Sat, 15 Feb 2020 10:28:41 +0000 Date: Sat, 15 Feb 2020 10:28:39 +0000 Message-ID: <868sl46t60.wl-maz@kernel.org> From: Marc Zyngier To: Robin Murphy Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Julien Thierry , Suzuki K Poulose Subject: Re: [PATCH 1/2] KVM: arm64: Add PMU event filtering infrastructure In-Reply-To: References: <20200214183615.25498-1-maz@kernel.org> <20200214183615.25498-2-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Fri, 14 Feb 2020 22:01:01 +0000, Robin Murphy wrote: Hi Robin, > > Hi Marc, > > On 2020-02-14 6:36 pm, Marc Zyngier wrote: > [...] > > @@ -585,6 +585,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > > pmc->idx != ARMV8_PMU_CYCLE_IDX) > > return; > > + /* > > + * If we have a filter in place and that the event isn't allowed, do > > + * not install a perf event either. > > + */ > > + if (vcpu->kvm->arch.pmu_filter && > > + !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) > > + return; > > If I'm reading the derivation of eventsel right, this will end up > treating cycle counter events (aliased to SW_INCR) differently from > CPU_CYCLES, which doesn't seem desirable. Indeed, this doesn't look quite right. Looking at the description of event 0x11, it doesn't seem to count exactly like the cycle counter (there are a number of PMCR controls affecting it). But none of these actually apply to our PMU emulation (no secure mode, and the idea of dealing with virtual EL2 in the context of the PMU is... not appealing). Now, given that we implement the cycle counter with event 0x11 anyway, I don't think there is any reason to deal with them separately. > Also, if the user did try to blacklist SW_INCR for ridiculous > reasons, we'd need to special-case kvm_pmu_software_increment() to > make it (not) work as expected, right? I thought of that one, and couldn't see a reason to blacklist it (after all, the guest could also increment a variable) and send itself an interrupt. I'm tempted to simply document that event 0 is never filtered. Thanks, M. -- Jazz is not dead, it just smells funny.