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<868srxnlk8.wl-maz@kernel.org> From: Marc Zyngier To: Aleix Roca Nonell Subject: Re: [PATCH 2/6] irqchip: Add Realtek RTD129x intc driver In-Reply-To: <20190812082648.GA3694@rocks> References: <20190707132256.GC13340@arks.localdomain> <5efa2ccb-9659-443c-7986-8ceb01aa64b9@arm.com> <20190812082648.GA3694@rocks> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: Approximate MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190813_081549_069906_C67E00C3 X-CRM114-Status: GOOD ( 41.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Jason Cooper , linux-kernel@vger.kernel.org, Rob Herring , Matthias Brugger , Thomas Gleixner , Andreas =?UTF-8?B?RsOkcmJlcg==?= , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCAxMiBBdWcgMjAxOSAwOToyNjo0OCArMDEwMCwKQWxlaXggUm9jYSBOb25lbGwgPGtl cm5lbHJvY2tzQGdtYWlsLmNvbT4gd3JvdGU6Cj4gCj4gSGkgTWFyayBhbmQgZXZlcnlvbmUhIFNv cnJ5IGZvciB0aGUgbGFyZ2UgZGVsYXksIEknbSBkb2luZyB0aGlzIGluIG15Cj4gZnJlZSB0aW1l LCB3aGljaCBpcyBub3QgdGhhdCBhYnVuZGFudC4gSW4gdGhpcyBtYWlsLCBJJ20gZm9jdXNpbmcg b25seQo+IG9uIHRoZSBsYXJnZXN0IGNoYW5nZSBtZW50aW9uZWQgYnkgTWFyay4gSSB3aWxsIGFu c3dlciB0aGUgcmVzdCBsYXRlci4KPiAKPiBPbiBNb24sIEp1bCAwOCwgMjAxOSBhdCAxMDozNjox NEFNICswMTAwLCBNYXJjIFp5bmdpZXIgd3JvdGU6Cj4gPiBPbiAwNy8wNy8yMDE5IDE0OjIyLCBB bGVpeCBSb2NhIE5vbmVsbCB3cm90ZToKPiA+ID4gVGhpcyBkcml2ZXIgYWRkcyBzdXBwb3J0IGZv ciB0aGUgUlREMTI5NiBhbmQgUlREMTI5NSBpbnRlcnJ1cHQKPiA+ID4gY29udHJvbGxlciAoaW50 YykuIEl0IGlzIGJhc2VkIG9uIGJvdGggdGhlIEJQSS1TSU5PVk9JUCBwcm9qZWN0IGFuZAo+ID4g PiBBbmRyZWFzIEbDpHJiZXIncyBwcmV2aW91cyBhdHRlbXB0IHRvIHN1Ym1pdCBhIHNpbWlsYXIg ZHJpdmVyLgo+ID4gPiAKPiA+ID4gVGhlcmUgaXMgY3VycmVudGx5IG5vIHB1YmxpY2x5IGF2YWls YWJsZSBkYXRhc2hlZXQgb24gdGhpcyBTb0MgYW5kIHRoZQo+ID4gPiBleGFjdCBiZWhhdmlvdXIg b2YgdGhlIHJlZ2lzdGVycyBjb250cm9sbGluZyB0aGUgaW50YyByZW1haW4gdW5jZXJ0YWluLgo+ ID4gPiAKPiA+ID4gVGhpcyBkcml2ZXIgY29udHJvbHMgdHdvIGludGNzOiAiaXNvIiBhbmQgIm1p c2MiLiBFYWNoIGludGMgaGFzIGl0cyBvd24KPiA+ID4gSW50ZXJydXB0IEVuYWJsZSBSZWdpc3Rl ciAoSUVSKSBhbmQgSW50ZXJydXB0IFN0YXR1cyBSZXNnaXN0ZXIgKElTUikuCj4gPiAKPiA+IFJl Z2lzdGVyCj4gPiAKPiA+ID4gSG93ZXZlciwgbm90IGFsbCAibWlzYyIgaW50YyBpcnFzIGhhdmUg dGhlIHNhbWUgb2Zmc2V0cyBmb3IgYm90aCBJU1IgYW5kCj4gPiA+IElFUi4gRm9yIHRoaXMgcmVh c29uIGFuIElTUiB0byBJRVIgb2Zmc2V0cyB0YWJsZSBpcyBkZWZpbmVkLgo+ID4gPiAKPiA+ID4g VGhlIGRyaXZlciBjYXRjaGVzIHRoZSBJRVIgdmFsdWUgdG8gcmVkdWNlIGFjY2Vzc2VzIHRvIHRo ZSB0YWJsZSBpbnNpZGUgdGhlCj4gPiA+IGludGVycnVwdCBoYW5kbGVyLiBBY3R1YWxseSwgdGhl IGRyaXZlciBzdG9yZXMgdGhlIElTUiBvZmZzZXRzIG9mIGN1cnJlbnRseQo+ID4gPiBlbmFibGVk IGludGVycnVwdHMgaW4gYSB2YXJpYWJsZS4KPiA+ID4gCj4gPiA+IFNpZ25lZC1vZmYtYnk6IEFs ZWl4IFJvY2EgTm9uZWxsIDxrZXJuZWxyb2Nrc0BnbWFpbC5jb20+Cj4gPiAKPiA+IEkgZXhwZWN0 IEFuZHJlYXMgYW5kIHlvdSB0byBzb3J0IHRoZSBhdHRyaWJ1dGlvbiBpc3N1ZS4gSSdtIGNlcnRh aW5seQo+ID4gbm90IGdvaW5nIHRvIHRha2UgdGhpcyBpbiBpZiB0aGluZ3MgYXJlIHVuY2xlYXIu Cj4gPiAKPiA+ID4gLS0tCj4gPiA+ICBkcml2ZXJzL2lycWNoaXAvTWFrZWZpbGUgICAgICB8ICAg MSArCj4gPiA+ICBkcml2ZXJzL2lycWNoaXAvaXJxLXJ0ZDEyOXguYyB8IDM3MSArKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrCj4gPiA+ICAyIGZpbGVzIGNoYW5nZWQsIDM3MiBpbnNl cnRpb25zKCspCj4gPiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQgZHJpdmVycy9pcnFjaGlwL2lycS1y dGQxMjl4LmMKPiA+ID4gCj4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2lycWNoaXAvTWFrZWZp bGUgYi9kcml2ZXJzL2lycWNoaXAvTWFrZWZpbGUKPiA+ID4gaW5kZXggNjA2YTAwM2EwMDAwLi4w Njg5YzM5NTYyNTAgMTAwNjQ0Cj4gPiA+IC0tLSBhL2RyaXZlcnMvaXJxY2hpcC9NYWtlZmlsZQo+ ID4gPiArKysgYi9kcml2ZXJzL2lycWNoaXAvTWFrZWZpbGUKPiA+ID4gQEAgLTEwMCwzICsxMDAs NCBAQCBvYmotJChDT05GSUdfTUFERVJBX0lSUSkJCSs9IGlycS1tYWRlcmEubwo+ID4gPiAgb2Jq LSQoQ09ORklHX0xTMVhfSVJRKQkJCSs9IGlycS1sczF4Lm8KPiA+ID4gIG9iai0kKENPTkZJR19U SV9TQ0lfSU5UUl9JUlFDSElQKQkrPSBpcnEtdGktc2NpLWludHIubwo+ID4gPiAgb2JqLSQoQ09O RklHX1RJX1NDSV9JTlRBX0lSUUNISVApCSs9IGlycS10aS1zY2ktaW50YS5vCj4gPiA+ICtvYmot JChDT05GSUdfQVJDSF9SRUFMVEVLKQkJKz0gaXJxLXJ0ZDEyOXgubwo+ID4gPiBkaWZmIC0tZ2l0 IGEvZHJpdmVycy9pcnFjaGlwL2lycS1ydGQxMjl4LmMgYi9kcml2ZXJzL2lycWNoaXAvaXJxLXJ0 ZDEyOXguYwo+ID4gPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+ID4gPiBpbmRleCAwMDAwMDAwMDAw MDAuLjc2MzU4Y2E1MGYxMAo+ID4gPiAtLS0gL2Rldi9udWxsCj4gPiA+ICsrKyBiL2RyaXZlcnMv aXJxY2hpcC9pcnEtcnRkMTI5eC5jCj4gPiA+IEBAIC0wLDAgKzEsMzcxIEBACj4gPiA+ICsvLyBT UERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMAo+ID4gPiArCj4gPiA+ICsjaW5jbHVkZSA8 bGludXgvaXJxY2hpcC5oPgo+ID4gPiArI2luY2x1ZGUgPGxpbnV4L29mLmg+Cj4gPiA+ICsjaW5j bHVkZSA8bGludXgvb2ZfYWRkcmVzcy5oPgo+ID4gPiArI2luY2x1ZGUgPGxpbnV4L29mX2lycS5o Pgo+ID4gPiArI2luY2x1ZGUgPGxpbnV4L2lycWRvbWFpbi5oPgo+ID4gPiArI2luY2x1ZGUgPGxp bnV4L2lvLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvc3BpbmxvY2suaD4KPiA+ID4gKyNpbmNs dWRlIDxsaW51eC9pcnFjaGlwLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvYml0cy5oPgo+ID4g PiArI2luY2x1ZGUgPGxpbnV4L2lycWNoaXAvY2hhaW5lZF9pcnEuaD4KPiA+ID4gKwo+ID4gPiAr I2RlZmluZSBSVEQxMjlYX0lOVENfTlJfSVJRUyAzMgo+ID4gPiArI2RlZmluZSBERVZfTkFNRSAi UlREMTI5Nl9JTlRDIgo+ID4gPiArCj4gPiA+ICsvKgo+ID4gPiArICogVGhpcyBpbnRlcnJ1cHQg Y29udHJvbGxlciAoaGVyZWluYWZ0ZXIgaW50YykgZHJpdmVyIGNvbnRyb2xzIHR3byBpbnRjczog ImlzbyIKPiA+ID4gKyAqIGFuZCAibWlzYyIuIEVhY2ggaW50YyBoYXMgaXRzIG93biBJbnRlcnJ1 cHQgRW5hYmxlIFJlZ2lzdGVyIChJRVIpIGFuZAo+ID4gPiArICogSW50ZXJydXB0IFN0YXR1cyBS ZXNnaXN0ZXIgKElTUikuIEhvd2V2ZXIsIG5vdCBhbGwgIm1pc2MiIGludGMgaXJxcyBoYXZlIHRo ZQo+ID4gPiArICogc2FtZSBvZmZzZXRzIGZvciBib3RoIElTUiBhbmQgSUVSLiBGb3IgdGhpcyBy ZWFzb24gYW4gSVNSIHRvIElFUiBvZmZzZXRzCj4gPiA+ICsgKiB0YWJsZSBpcyBkZWZpbmVkLiBB bHNvLCB0byByZWR1Y2UgYWNjZXNzZXMgdG8gdGhpcyB0YWJsZSBpbiB0aGUgaW50ZXJydXB0Cj4g PiA+ICsgKiBoYW5kbGVyLCB0aGUgZHJpdmVyIHN0b3JlcyB0aGUgSVNSIG9mZnNldHMgb2YgY3Vy cmVudGx5IGVuYWJsZWQgaW50ZXJydXB0cyBpbgo+ID4gPiArICogYSB2YXJpYWJsZS4KPiA+ID4g KyAqLwo+ID4gPiArCj4gPiA+ICtlbnVtIG1pc2NfaW50X2VuIHsKPiA+ID4gKwlNSVNDX0lOVF9G QUlMCQk9IDB4RkYsCj4gPiA+ICsJTUlTQ19JTlRfUlZECQk9IDB4RkUsCj4gPiA+ICsJTUlTQ19J TlRfRU5fRkFOCQk9IDI5LAo+ID4gPiArCU1JU0NfSU5UX0VOX0kyQzMJPSAyOCwKPiA+ID4gKwlN SVNDX0lOVF9FTl9HU1BJCT0gMjcsCj4gPiA+ICsJTUlTQ19JTlRfRU5fSTJDMgk9IDI2LAo+ID4g PiArCU1JU0NfSU5UX0VOX1NDMAkJPSAyNCwKPiA+ID4gKwlNSVNDX0lOVF9FTl9MU0FEQzEJPSAy MiwKPiA+ID4gKwlNSVNDX0lOVF9FTl9MU0FEQzAJPSAyMSwKPiA+ID4gKwlNSVNDX0lOVF9FTl9H UElPREEJPSAyMCwKPiA+ID4gKwlNSVNDX0lOVF9FTl9HUElPQQk9IDE5LAo+ID4gPiArCU1JU0Nf SU5UX0VOX0kyQzQJPSAxNSwKPiA+ID4gKwlNSVNDX0lOVF9FTl9JMkM1CT0gMTQsCj4gPiA+ICsJ TUlTQ19JTlRfRU5fUlRDX0RBVEEJPSAxMiwKPiA+ID4gKwlNSVNDX0lOVF9FTl9SVENfSE9VUgk9 IDExLAo+ID4gPiArCU1JU0NfSU5UX0VOX1JUQ19NSU4JPSAxMCwKPiA+ID4gKwlNSVNDX0lOVF9F Tl9VUjIJCT0gNywKPiA+ID4gKwlNSVNDX0lOVF9FTl9VUjJfVE8JPSA2LAo+ID4gPiArCU1JU0Nf SU5UX0VOX1VSMV9UTwk9IDUsCj4gPiA+ICsJTUlTQ19JTlRfRU5fVVIxCQk9IDMsCj4gPiA+ICt9 Owo+ID4gPiArCj4gPiA+ICtlbnVtIGlzb19pbnRfZW4gewo+ID4gPiArCUlTT19JTlRfRkFJTAkJ PSAweEZGLAo+ID4gPiArCUlTT19JTlRfUlZECQk9IDB4RkUsCj4gPiA+ICsJSVNPX0lOVF9FTl9J MkMxX1JFUQk9IDMxLAo+ID4gPiArCUlTT19JTlRfRU5fR1BIWV9BVgk9IDMwLAo+ID4gPiArCUlT T19JTlRfRU5fR1BIWV9EVgk9IDI5LAo+ID4gPiArCUlTT19JTlRfRU5fR1BJT0RBCT0gMjAsCj4g PiA+ICsJSVNPX0lOVF9FTl9HUElPQQk9IDE5LAo+ID4gPiArCUlTT19JTlRfRU5fUlRDX0FMQVJN CT0gMTMsCj4gPiA+ICsJSVNPX0lOVF9FTl9SVENfSFNFQwk9IDEyLAo+ID4gPiArCUlTT19JTlRf RU5fSTJDMQkJPSAxMSwKPiA+ID4gKwlJU09fSU5UX0VOX0kyQzAJCT0gOCwKPiA+ID4gKwlJU09f SU5UX0VOX0lSREEJCT0gNSwKPiA+ID4gKwlJU09fSU5UX0VOX1VSMAkJPSAyLAo+ID4gPiArfTsK PiA+ID4gKwo+ID4gPiArdW5zaWduZWQgY2hhciBydGQxMjl4X2ludGNfZW5hYmxlX21hcF9taXNj W1JURDEyOVhfSU5UQ19OUl9JUlFTXSA9IHsKPiA+ID4gKwlNSVNDX0lOVF9GQUlMLAkJLyogQml0 MCAqLwo+ID4gPiArCU1JU0NfSU5UX0ZBSUwsCQkvKiBCaXQxICovCj4gPiA+ICsJTUlTQ19JTlRf UlZELAkJLyogQml0MiAqLwo+ID4gPiArCU1JU0NfSU5UX0VOX1VSMSwJLyogQml0MyAqLwo+ID4g PiArCU1JU0NfSU5UX0ZBSUwsCQkvKiBCaXQ0ICovCj4gPiA+ICsJTUlTQ19JTlRfRU5fVVIxX1RP LAkvKiBCaXQ1ICovCj4gPiA+ICsJTUlTQ19JTlRfUlZELAkJLyogQml0NiAqLwo+ID4gPiArCU1J U0NfSU5UX1JWRCwJCS8qIEJpdDcgKi8KPiA+ID4gKwlNSVNDX0lOVF9FTl9VUjIsCS8qIEJpdDgg Ki8KPiA+ID4gKwlNSVNDX0lOVF9SVkQsCQkvKiBCaXQ5ICovCj4gPiA+ICsJTUlTQ19JTlRfRU5f UlRDX01JTiwJLyogQml0MTAgKi8KPiA+ID4gKwlNSVNDX0lOVF9FTl9SVENfSE9VUiwJLyogQml0 MTEgKi8KPiA+ID4gKwlNSVNDX0lOVF9FTl9SVENfREFUQSwJLyogQml0MTIgKi8KPiA+ID4gKwlN SVNDX0lOVF9FTl9VUjJfVE8sCS8qIEJpdDEzICovCj4gPiA+ICsJTUlTQ19JTlRfRU5fSTJDNSwJ LyogQml0MTQgKi8KPiA+ID4gKwlNSVNDX0lOVF9FTl9JMkM0LAkvKiBCaXQxNSAqLwo+ID4gPiAr CU1JU0NfSU5UX0ZBSUwsCQkvKiBCaXQxNiAqLwo+ID4gPiArCU1JU0NfSU5UX0ZBSUwsCQkvKiBC aXQxNyAqLwo+ID4gPiArCU1JU0NfSU5UX0ZBSUwsCQkvKiBCaXQxOCAqLwo+ID4gPiArCU1JU0Nf SU5UX0VOX0dQSU9BLAkvKiBCaXQxOSAqLwo+ID4gPiArCU1JU0NfSU5UX0VOX0dQSU9EQSwJLyog Qml0MjAgKi8KPiA+ID4gKwlNSVNDX0lOVF9FTl9MU0FEQzAsCS8qIEJpdDIxICovCj4gPiA+ICsJ TUlTQ19JTlRfRU5fTFNBREMxLAkvKiBCaXQyMiAqLwo+ID4gPiArCU1JU0NfSU5UX0VOX0kyQzMs CS8qIEJpdDIzICovCj4gPiA+ICsJTUlTQ19JTlRfRU5fU0MwLAkvKiBCaXQyNCAqLwo+ID4gPiAr CU1JU0NfSU5UX0ZBSUwsCQkvKiBCaXQyNSAqLwo+ID4gPiArCU1JU0NfSU5UX0VOX0kyQzIsCS8q IEJpdDI2ICovCj4gPiA+ICsJTUlTQ19JTlRfRU5fR1NQSSwJLyogQml0MjcgKi8KPiA+ID4gKwlN SVNDX0lOVF9GQUlMLAkJLyogQml0MjggKi8KPiA+ID4gKwlNSVNDX0lOVF9FTl9GQU4sCS8qIEJp dDI5ICovCj4gPiA+ICsJTUlTQ19JTlRfRkFJTCwJCS8qIEJpdDMwICovCj4gPiA+ICsJTUlTQ19J TlRfRkFJTAkJLyogQml0MzEgKi8KPiA+ID4gK307Cj4gPiA+ICsKPiA+ID4gK3Vuc2lnbmVkIGNo YXIgcnRkMTI5eF9pbnRjX2VuYWJsZV9tYXBfaXNvW1JURDEyOVhfSU5UQ19OUl9JUlFTXSA9IHsK PiA+ID4gKwlJU09fSU5UX0ZBSUwsCQkvKiBCaXQwICovCj4gPiA+ICsJSVNPX0lOVF9SVkQsCQkv KiBCaXQxICovCj4gPiA+ICsJSVNPX0lOVF9FTl9VUjAsCQkvKiBCaXQyICovCj4gPiA+ICsJSVNP X0lOVF9GQUlMLAkJLyogQml0MyAqLwo+ID4gPiArCUlTT19JTlRfRkFJTCwJCS8qIEJpdDQgKi8K PiA+ID4gKwlJU09fSU5UX0VOX0lSREEsCS8qIEJpdDUgKi8KPiA+ID4gKwlJU09fSU5UX0ZBSUws CQkvKiBCaXQ2ICovCj4gPiA+ICsJSVNPX0lOVF9SVkQsCQkvKiBCaXQ3ICovCj4gPiA+ICsJSVNP X0lOVF9FTl9JMkMwLAkvKiBCaXQ4ICovCj4gPiA+ICsJSVNPX0lOVF9SVkQsCQkvKiBCaXQ5ICov Cj4gPiA+ICsJSVNPX0lOVF9GQUlMLAkJLyogQml0MTAgKi8KPiA+ID4gKwlJU09fSU5UX0VOX0ky QzEsCS8qIEJpdDExICovCj4gPiA+ICsJSVNPX0lOVF9FTl9SVENfSFNFQywJLyogQml0MTIgKi8K PiA+ID4gKwlJU09fSU5UX0VOX1JUQ19BTEFSTSwJLyogQml0MTMgKi8KPiA+ID4gKwlJU09fSU5U X0ZBSUwsCQkvKiBCaXQxNCAqLwo+ID4gPiArCUlTT19JTlRfRkFJTCwJCS8qIEJpdDE1ICovCj4g PiA+ICsJSVNPX0lOVF9GQUlMLAkJLyogQml0MTYgKi8KPiA+ID4gKwlJU09fSU5UX0ZBSUwsCQkv KiBCaXQxNyAqLwo+ID4gPiArCUlTT19JTlRfRkFJTCwJCS8qIEJpdDE4ICovCj4gPiA+ICsJSVNP X0lOVF9FTl9HUElPQSwJLyogQml0MTkgKi8KPiA+ID4gKwlJU09fSU5UX0VOX0dQSU9EQSwJLyog Qml0MjAgKi8KPiA+ID4gKwlJU09fSU5UX1JWRCwJCS8qIEJpdDIxICovCj4gPiA+ICsJSVNPX0lO VF9SVkQsCQkvKiBCaXQyMiAqLwo+ID4gPiArCUlTT19JTlRfUlZELAkJLyogQml0MjMgKi8KPiA+ ID4gKwlJU09fSU5UX1JWRCwJCS8qIEJpdDI0ICovCj4gPiA+ICsJSVNPX0lOVF9GQUlMLAkJLyog Qml0MjUgKi8KPiA+ID4gKwlJU09fSU5UX0ZBSUwsCQkvKiBCaXQyNiAqLwo+ID4gPiArCUlTT19J TlRfRkFJTCwJCS8qIEJpdDI3ICovCj4gPiA+ICsJSVNPX0lOVF9GQUlMLAkJLyogQml0MjggKi8K PiA+ID4gKwlJU09fSU5UX0VOX0dQSFlfRFYsCS8qIEJpdDI5ICovCj4gPiA+ICsJSVNPX0lOVF9F Tl9HUEhZX0FWLAkvKiBCaXQzMCAqLwo+ID4gPiArCUlTT19JTlRfRU5fSTJDMV9SRVEJLyogQml0 MzEgKi8KPiA+ID4gK307Cj4gPiA+ICsKPiA+ID4gK3N0cnVjdCBydGQxMjl4X2ludGNfZGF0YSB7 Cj4gPiA+ICsJdm9pZCBfX2lvbWVtCQkqdW5tYXNrOwo+ID4gPiArCXZvaWQgX19pb21lbQkJKmlz cjsKPiA+ID4gKwl2b2lkIF9faW9tZW0JCSppZXI7Cj4gPiA+ICsJdTMyCQkJaWVyX2NhY2hlZDsK PiA+ID4gKwl1MzIJCQlpc3JfZW47Cj4gPiA+ICsJcmF3X3NwaW5sb2NrX3QJCWxvY2s7Cj4gPiA+ ICsJdW5zaWduZWQgaW50CQlwYXJlbnRfaXJxOwo+ID4gPiArCWNvbnN0IHVuc2lnbmVkIGNoYXIJ KmVuX21hcDsKPiA+ID4gK307Cj4gPiA+ICsKPiA+ID4gK3N0YXRpYyBzdHJ1Y3QgaXJxX2RvbWFp biAqcnRkMTI5eF9pbnRjX2RvbWFpbjsKPiA+ID4gKwo+ID4gPiArc3RhdGljIHZvaWQgcnRkMTI5 eF9pbnRjX2lycV9oYW5kbGUoc3RydWN0IGlycV9kZXNjICpkZXNjKQo+ID4gPiArewo+ID4gPiAr CXN0cnVjdCBydGQxMjl4X2ludGNfZGF0YSAqcHJpdiA9IGlycV9kZXNjX2dldF9oYW5kbGVyX2Rh dGEoZGVzYyk7Cj4gPiA+ICsJc3RydWN0IGlycV9jaGlwICpjaGlwID0gaXJxX2Rlc2NfZ2V0X2No aXAoZGVzYyk7Cj4gPiA+ICsJdW5zaWduZWQgaW50IGxvY2FsX2lycTsKPiA+ID4gKwl1MzIgc3Rh dHVzOwo+ID4gPiArCWludCBpOwo+ID4gPiArCj4gPiA+ICsJY2hhaW5lZF9pcnFfZW50ZXIoY2hp cCwgZGVzYyk7Cj4gPiA+ICsKPiA+ID4gKwlyYXdfc3Bpbl9sb2NrKCZwcml2LT5sb2NrKTsKPiA+ ID4gKwlzdGF0dXMgPSByZWFkbF9yZWxheGVkKHByaXYtPmlzcik7Cj4gPiA+ICsJc3RhdHVzICY9 IHByaXYtPmlzcl9lbjsKPiA+ID4gKwlyYXdfc3Bpbl91bmxvY2soJnByaXYtPmxvY2spOwo+ID4g Cj4gPiBXaGF0IGlzIHRoaXMgbG9jayBwcm90ZWN0aW5nPyBpc3JfZW4/Cj4gPiAKPiA+ID4gKwo+ ID4gPiArCXdoaWxlIChzdGF0dXMpIHsKPiA+ID4gKwkJaSA9IF9fZmZzKHN0YXR1cyk7Cj4gPiA+ ICsJCXN0YXR1cyAmPSB+QklUKGkpOwo+ID4gPiArCj4gPiA+ICsJCWxvY2FsX2lycSA9IGlycV9m aW5kX21hcHBpbmcocnRkMTI5eF9pbnRjX2RvbWFpbiwgaSk7Cj4gPiA+ICsJCWlmIChsaWtlbHko bG9jYWxfaXJxKSkgewo+ID4gPiArCQkJaWYgKCFnZW5lcmljX2hhbmRsZV9pcnEobG9jYWxfaXJx KSkKPiA+ID4gKwkJCQl3cml0ZWxfcmVsYXhlZChCSVQoaSksIHByaXYtPmlzcik7Cj4gPiAKPiA+ IFdoYXQgYXJlIHRoZSB3cml0ZSBzZW1hbnRpY3Mgb2YgdGhlIElTUiByZWdpc3Rlcj8gSG90IGJp dCBjbGVhcj8gSG93Cj4gPiBkb2VzIGl0IHdvcmsgc2luY2UgbWFzaygpIGRvZXMgdGhlIHNhbWUg dGhpbmc/IENsZWFybHksIHNvbWV0aGluZyBpcwo+ID4gd3JvbmcgaGVyZS4KPiAKPiBTb3JyeSBi dXQgSSBoYXZlIG5vdCBiZWVuIGFibGUgdG8gZm91bmQgdGhlIGRlZmluaXRpb24gb2YgImhvdCBi aXQKPiBjbGVhciIsIGNvdWxkIHlvdSBleHBsYWluIGl0PyBBbnl3YXlzLCB5b3Ugd2VyZSByaWdo dCwgYXBwYXJlbnRseSB0aGUKPiBtYXNrL3VubWFzayBjb2RlIHdlcmUgZG9pbmcgbm90aGluZyB1 c2VmdWwuIE1vcmUgb24gdGhpcyBiZWxvdy4KCkEgaG90LWJpdCBjbGVhciAob3Igc2V0KSBpcyBh IHJlZ2lzdGVyIHdoZXJlIHRvIHdyaXRlIHRoZSBiaXRzIHRoYXQKeW91IHdhbnQgdG8gY2xlYXIg KG9yIHNldCksIGxlYXZpbmcgYWxvbmUgdGhlIGJpdHMgdGhhdCBhcmUgd3JpdHRlbiBhcwp6ZXJv LiBGb3IgZXhhbXBsZToKClJFRyA9IDB4RkZGRgpjbGVhcl9yZWcoMHgxMDAxKQpSRUcgPSAweDdG RkUKc2V0X3JlZygweDEwMDApClJFRyA9IDB4RkZGRQoKSXQgaXMgZXh0cmVtZWx5IHVzZWZ1bCBm b3IgcmVnaXN0ZXJzIHRoYXQgbmVlZCB0byBiZSBhY2Nlc3NlZApjb25jdXJyZW50bHkgKHRoZSBH SUMgdXNlcyB0aGF0IGEgbG90LCBmb3IgZXhhbXBsZSkuCgo+IAo+ID4gCj4gPiA+ICsJCX0gZWxz ZSB7Cj4gPiA+ICsJCQloYW5kbGVfYmFkX2lycShkZXNjKTsKPiA+ID4gKwkJfQo+ID4gPiArCX0K PiA+ID4gKwo+ID4gPiArCWNoYWluZWRfaXJxX2V4aXQoY2hpcCwgZGVzYyk7Cj4gPiA+ICt9Cj4g PiA+ICsKPiA+ID4gK3N0YXRpYyB2b2lkIHJ0ZDEyOXhfaW50Y19tYXNrKHN0cnVjdCBpcnFfZGF0 YSAqZGF0YSkKPiA+ID4gK3sKPiA+ID4gKwlzdHJ1Y3QgcnRkMTI5eF9pbnRjX2RhdGEgKnByaXYg PSBpcnFfZGF0YV9nZXRfaXJxX2NoaXBfZGF0YShkYXRhKTsKPiA+ID4gKwo+ID4gPiArCXdyaXRl bF9yZWxheGVkKEJJVChkYXRhLT5od2lycSksIHByaXYtPmlzcik7Cj4gPiA+ICt9Cj4gPiA+ICsK PiA+ID4gK3N0YXRpYyB2b2lkIHJ0ZDEyOXhfaW50Y191bm1hc2soc3RydWN0IGlycV9kYXRhICpk YXRhKQo+ID4gPiArewo+ID4gPiArCXN0cnVjdCBydGQxMjl4X2ludGNfZGF0YSAqcHJpdiA9IGly cV9kYXRhX2dldF9pcnFfY2hpcF9kYXRhKGRhdGEpOwo+ID4gPiArCj4gPiA+ICsJd3JpdGVsX3Jl bGF4ZWQoQklUKGRhdGEtPmh3aXJxKSwgcHJpdi0+dW5tYXNrKTsKPiA+IAo+ID4gV2hhdCBlZmZl Y3QgZG9lcyB0aGlzIGhhdmUgb24gdGhlIGlzciByZWdpc3Rlcj8gVGhlIHdob2xlIG1hc2svdW5t YXNrCj4gPiB0aGluZyBzZWVtcyB0byBiZSBwcmV0dHkgZG9kZ3kuLi4KPiA+IAo+ID4gPiArfQo+ ID4gPiArCj4gPiA+ICtzdGF0aWMgdm9pZCBydGQxMjl4X2ludGNfZW5hYmxlKHN0cnVjdCBpcnFf ZGF0YSAqZGF0YSkKPiA+ID4gK3sKPiA+ID4gKwlzdHJ1Y3QgcnRkMTI5eF9pbnRjX2RhdGEgKnBy aXYgPSBpcnFfZGF0YV9nZXRfaXJxX2NoaXBfZGF0YShkYXRhKTsKPiA+ID4gKwl1bnNpZ25lZCBs b25nIGZsYWdzOwo+ID4gPiArCXU4IGVuX29mZnNldDsKPiA+ID4gKwo+ID4gPiArCWVuX29mZnNl dCA9IHByaXYtPmVuX21hcFtkYXRhLT5od2lycV07Cj4gPiA+ICsKPiA+ID4gKwlpZiAoKGVuX29m ZnNldCAhPSBNSVNDX0lOVF9SVkQpICYmIChlbl9vZmZzZXQgIT0gTUlTQ19JTlRfRkFJTCkpIHsK PiA+ID4gKwkJcmF3X3NwaW5fbG9ja19pcnFzYXZlKCZwcml2LT5sb2NrLCBmbGFncyk7Cj4gPiA+ ICsKPiA+ID4gKwkJcHJpdi0+aXNyX2VuIHw9IEJJVChkYXRhLT5od2lycSk7Cj4gPiA+ICsJCXBy aXYtPmllcl9jYWNoZWQgfD0gQklUKGVuX29mZnNldCk7Cj4gPiA+ICsJCXdyaXRlbF9yZWxheGVk KHByaXYtPmllcl9jYWNoZWQsIHByaXYtPmllcik7Cj4gPiA+ICsKPiA+ID4gKwkJcmF3X3NwaW5f dW5sb2NrX2lycXJlc3RvcmUoJnByaXYtPmxvY2ssIGZsYWdzKTsKPiA+ID4gKwl9IGVsc2UgaWYg KGVuX29mZnNldCA9PSBNSVNDX0lOVF9GQUlMKSB7Cj4gPiA+ICsJCXByX2VycigiWyVzXSBFbmFi bGUgaXJxKCVsdSkgZmFpbGVkXG4iLCBERVZfTkFNRSwgZGF0YS0+aHdpcnEpOwo+ID4gPiArCX0K PiA+ID4gK30KPiA+ID4gKwo+ID4gPiArc3RhdGljIHZvaWQgcnRkMTI5eF9pbnRjX2Rpc2FibGUo c3RydWN0IGlycV9kYXRhICpkYXRhKQo+ID4gPiArewo+ID4gPiArCXN0cnVjdCBydGQxMjl4X2lu dGNfZGF0YSAqcHJpdiA9IGlycV9kYXRhX2dldF9pcnFfY2hpcF9kYXRhKGRhdGEpOwo+ID4gPiAr CXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gPiA+ICsJdTggZW5fb2Zmc2V0Owo+ID4gPiArCj4gPiA+ ICsJZW5fb2Zmc2V0ID0gcHJpdi0+ZW5fbWFwW2RhdGEtPmh3aXJxXTsKPiA+ID4gKwo+ID4gPiAr CWlmICgoZW5fb2Zmc2V0ICE9IE1JU0NfSU5UX1JWRCkgJiYgKGVuX29mZnNldCAhPSBNSVNDX0lO VF9GQUlMKSkgewo+ID4gPiArCQlyYXdfc3Bpbl9sb2NrX2lycXNhdmUoJnByaXYtPmxvY2ssIGZs YWdzKTsKPiA+ID4gKwo+ID4gPiArCQlwcml2LT5pc3JfZW4gJj0gfkJJVChkYXRhLT5od2lycSk7 Cj4gPiA+ICsJCXByaXYtPmllcl9jYWNoZWQgJj0gfkJJVChlbl9vZmZzZXQpOwo+ID4gPiArCQl3 cml0ZWxfcmVsYXhlZChwcml2LT5pZXJfY2FjaGVkLCBwcml2LT5pZXIpOwo+ID4gPiArCj4gPiA+ ICsJCXJhd19zcGluX3VubG9ja19pcnFyZXN0b3JlKCZwcml2LT5sb2NrLCBmbGFncyk7Cj4gPiA+ ICsJfSBlbHNlIGlmIChlbl9vZmZzZXQgPT0gTUlTQ19JTlRfRkFJTCkgewo+ID4gPiArCQlwcl9l cnIoIlslc10gRGlzYWJsZSBpcnEoJWx1KSBmYWlsZWRcbiIsIERFVl9OQU1FLCBkYXRhLT5od2ly cSk7Cj4gPiA+ICsJfQo+ID4gPiArfQo+ID4gCj4gPiBTbyBoZXJlJ3MgYSB0aG91Z2h0OiBXaHkg ZG8gd2UgbmVlZCBhbGwgb2YgdGhpcz8gSWYgbWFzay91bm1hc2sgZG8gdGhlaXIKPiA+IGpvYiBj b3JyZWN0bHksIHdlIGNvdWxkIGp1c3QgZW5hYmxlIGFsbCBpbnRlcnJ1cHRzIGluIG9uZSBnbyAo anVzdCBhCj4gPiAzMmJpdCB3cml0ZSkgYXQgcHJvYmUgdGltZSwgYW5kIGxlYXZlIGFsbCBpbnRl cnJ1cHRzIG1hc2tlZCB1bnRpbCB0aGV5Cj4gPiBhcmUgaW4gdXNlLiBZb3UgY291bGQgdGhlbiBk cm9wIGFsbCB0aGVzZSBzaWxseSB0YWJsZXMgdGhhdCBkb24ndCBicmluZwo+ID4gbXVjaC4uLgo+ IAo+IFRoZSBpZGVhIG9mIGRyb3BwaW5nIGFsbCB0aG9zZSB0YWJsZXMgbG9vayByZWFsbHkgZ29v ZCB0byBtZSwgdGhhdAo+IHdvdWxkIGdyZWF0bHkgc2ltcGxpZnkgdGhlIGNvZGUhIEkgaGF2ZSBi ZWVuIHRyeWluZyB0byBtYXNrIGFsbAo+IGludGVycnVwdHMgb24gdGhlIHByb2JlIGZ1bmN0aW9u IHVzaW5nIHRoZSBJU1IgcmVnaXN0ZXIgYnV0IHdoaWxlCj4gZG9pbmcgc28sIEkgcmVhbGl6ZWQg dGhhdCBpdCBkb2VzIG5vdCB3b3JrLiBXcml0aW5nIHRvIElTUiBkb2VzIG5vdAo+IG1hc2sgaW50 ZXJydXB0cywgYXBwYXJlbnRseSBpdCBvbmx5IGFja25vd2xlZGdlcyB0aGVtIG9uY2UgdGhleSBo YXZlCj4gYmVlbiB0cmlnZ2VyZWQuIE9uIHRoZSBzY2Fyc2UgYXZhaWxhYmxlIGRvY3VtZW50YXRp b24gb2YgdGhpcyBTb2MgSQo+IGNhbm5vdCBmaW5kIGEgbWFzay1saWtlIHJlZ2lzdGVyLiBJdCBz ZWVtcyBpbnRlcnJ1cHRzIGFyZSBtYW5hZ2VkIHdpdGgKPiBhbiBJU1IgYW5kIGFuIElFUiByZWdp c3Rlci4gU28gaXQgc2hvdWxkIGJlIHBvc2libGUgdG8gdXNlIHRoZSBlbmFibGUKPiByZWdpc3Rl ciB0byBtYWtzL3VubWFzayBpbnN0ZWFkLiBUaGVzZSBkbyB3b3JrLiBIb3dldmVyLCB0aGF0IHdv dWxkCj4gbWVhbiB0aGF0IHdlIGhhdmUgdG8ga2VlcCB0aG9zZSB1Z2x5IHRhYmxlcy4KPiAKPiBO b25ldGhlbGVzcyB3ZSBtaWdodCBzdGlsbCBiZSBhYmxlIHRvIGRvIHNvbWV0aGluZyBlbHNlLiBQ bGVhc2UsCj4gY29ycmVjdCBtZSBpZiBJJ20gd3JvbmcsIGJ1dCBkbyB3ZSByZWFsbHkgbmVlZCB0 byBtYXNrL3VuYW1zayBpbiB0aGlzCj4gc2NlbmFyaW8/IFRoaXMgaXMgdGhlIGRldmlzZWQgYm9h cmQgbGF5b3V0Ogo+IAo+ICAgICAgICAgICAgKy0tLS0tLSsgICAgICAgKy0tLS0tLS0tLS0rICAg ICAgICstLS0tLS0tLS0rCj4gICAgICAgICAgICB8ICAgICAgfCAgICAgICB8ICAgICAgICAgIHwg ICAgICAgfCAgICAgICAgIHwKPiAgICAgICAgICAgIHwgVUFSVCB8LS0tLS0tLXwyICBJTlRDICAg fC0tLS0tLS18YyAgR0lDICAgfAo+ICAgICAgICAgICAgfCAgICAgIHwgICstLS0tfDEgICAgICAg ICB8ICArLS0tLXxiICAgICAgICB8Cj4gICAgICAgICAgICArLS0tLS0tKyAgfCArLS18MCAgICAg ICAgIHwgIHwgKy0tfGEgICAgICAgIHwKPiAgICAgICAgICAgICAgICAgICAgICB8IHwgIHwgICAg ICAgICAgfCAgfCB8ICB8ICAgICAgICAgfAo+ICAgICAgICAgICAgICAgICAgICAgIHwgfCAgKy0t LS0tLS0tLS0rICB8IHwgICstLS0tLS0tLS0rCj4gICAgICAgICAgICAgICAgICAgICAgfCAgICAg ICAgICAgICAgICAgIHwKPiAKPiBPbmNlIHRoZSBVQVJUIGdlbmVyYXRlcyBhbiBpbnRlcnJ1cHQg aXQgcGFzc2VzIHRocm91Z2ggdGhlIGxpbmUgMiBvZgo+IHRoZSBjdXN0b20gcmVhbHRlayBpbnRl cnJ1cHQgY29udG9sbGVyIGJlZm9yZSByZWFjaGluZyB0aGUgR0lDJ3MgbGluZQo+ICJjIi4gT24g dGhlIElOVEMgaW50ZXJydXB0IGhhbmRsZXIsIHdlIGNhbGwgY2hhaW5lZF9pcnFfZW50ZXIvZXhp dAo+IHRvIG1hc2svdW5tYXNrIHRoZSBHSUMncyAiYyIgbGluZS4gQmVjYXVzZSBhbGwgb2YgdGhp cyByZWFsdGVrIElOVEMKPiBpbnRlcnJ1cHQgbGluZXMgKDIsMSwwLC4uLikgYXJlIG11eGVkIG9u IHRoZSBHSUMncyBsaW5lICJjIiwgdGhpcwo+IG1lYW5zIHRoYXQgd2hpbGUgb24gdGhlIElOVEMg aW50ZXJydXB0IGhhbmRsZXIgaXQgaXMgbm90IHBvc3NpYmxlIHRvCj4gc2VuZCBmdXJ0aGVyIGlu dGVycnVwdHMgb24gdGhlIENQVS4gR2l2ZW4gdGhhdCBpbnRlcnJ1cHRzIGFyZSBtYXNrZWQKPiBv biB0aGUgR0lDLCBpdCBzZWVtcyBzYWZlIHRvIGp1c3QgcmVtb3ZlIElOVEMncyBtYXNrL3VubWFz ayBmdW5jdGlvbnMuCgpObywgdGhhdCdzIG5vdCB0cnVlLiBJZiB5b3UgY2Fubm90IG1hc2sgYW4g aW5kaXZpZHVhbCBpbnRlcnJ1cHQgYXQgdGhlCklOVEMgbGV2ZWwsIGl0IG1lYW5zIHRoYXQgdGhl IG9ubHkgd2F5IHRvIHN0b3AgYSBzY3JlYW1pbmcgaW50ZXJydXB0CihiZWNhdXNlIHRoZSBlbmRw b2ludCBoYXMgY3Jhc2hlZCBvciB0aGF0IHRoZSBrZXJuZWwgZG9lc24ndCBoYXZlIGEKZHJpdmVy IGZvciBpdCkgaXMgdG8gZGlzYWJsZSB0aGUgaW50ZXJydXB0IGF0IHRoZSBHSUMgbGV2ZWwsIGtp bGxpbmcKYWxsIHVzZXJzIG9mIHRoZSBJTlRDLiBBbHNvLCBiZWNhdXNlIHRoZSBjb3JlIGNvZGUg ZG9lc24ndCByZWFsbHkga25vdwp0aGF0IHRoZSBJTlRDIGlzIGJlaGluZCB0aGUgR0lDLCBpdCBj YW5ub3QgZG8gdGhhdCBhdXRvbWF0aWNhbGx5LgoKU28gaWYgeW91IGdldCBpbnRvIHRoYXQgc2l0 dWF0aW9uLCB5b3VyIHN5c3RlbSBpcyBkZWFkLiBCZWxpZXZlIGl0IG9yCm5vdCwgdGhhdCdzIG5v dCBzb21ldGhpbmcgSSB3YW50IHRvIHNlZS4gQW4gaXJxY2hpcCBkcml2ZXIgd2l0aG91dCBhCm1h c2sgY2FsbGJhY2sgaXMgYSBsb3NlIGdyZW5hZGUsIGFuZCB0aGUgcGluIGlzIGluIHlvdXIgcG9j a2V0LgoKPiBUaGVyZWZvcmUsIHRoZSBvbmx5IHdvcmsgdGhhdCB0aGlzIElOVEMgaGFuZGxlciB3 b3VsZCBuZWVkcyB0byBkbyBpcwo+IHRvIGFja25vd2xlZGdlIHRoZSBpbnRlcnJ1cHQgYnkgd3Jp dGluZyB0byB0aGUgSVNSLCB3aGljaCBpdCBjb3VsZCBiZQo+IGRvbmUgaW4gdGhlIHJlc3BlY3Rp dmUgaXJxX2FjayBjYWxsYmFjayBvZiBzdHJ1Y3QgaXJxX2NoaXAgaW5zdGVhZCBvZgo+IGluIHRo ZSBoYW5kbGVyIGJvZHkuCj4gCj4gSSBoYXZlIGltcGxlbWVudGVkIHRoaXMgc29sdXRpb24gYW5k IGl0IHNlZW1zIHRvIHdvcmsuIFdoYXQgZG8geW91Cj4gdGhpbms/IEknbSBtaXNzaW5nIHNvbWV0 aGluZyBjcnVjaWFsPwoKU2VlIGFib3ZlLiBZb3VyIHN5c3RlbSBpcyB0ZXJyaWJseSB1bnNhZmUu IE5vdywgSSdtIHByZXR0eSBzdXJlIHRoZQpSZWFsdGVrIGZvbGtzIGNvdWxkIGhlbHAgeW91IHRo ZXJlLiBPciB5b3UgY291bGQgc3RhcnQgdHJ5aW5nIHRvCnJldmVyc2UgZW5naW5lZXIgdGhlIHRo aW5nLCB3aGljaCBzaG91bGRuJ3QgcmVhbGx5IGhhcmQgKHRyeSBwb2tpbmcgYXQKdGhlIHJlZ2lz dGVycyBuZXh0IHRvIHRoZSBvbmVzIHlvdSBhbHJlYWR5IGhhdmUpLgoKVGhhbmtzLAoKCU0uCgot LSAKSmF6eiBpcyBub3QgZGVhZCwgaXQganVzdCBzbWVsbHMgZnVubnkuCgpfX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxp bmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3Rz LmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH 2/6] irqchip: Add Realtek RTD129x intc driver Date: Tue, 13 Aug 2019 16:15:35 +0100 Message-ID: <868srxnlk8.wl-maz@kernel.org> References: <20190707132256.GC13340@arks.localdomain> <5efa2ccb-9659-443c-7986-8ceb01aa64b9@arm.com> <20190812082648.GA3694@rocks> Mime-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <20190812082648.GA3694@rocks> Sender: linux-kernel-owner@vger.kernel.org To: Aleix Roca Nonell Cc: Andreas =?UTF-8?B?RsOkcmJlcg==?= , Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Matthias Brugger , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org On Mon, 12 Aug 2019 09:26:48 +0100, Aleix Roca Nonell wrote: > > Hi Mark and everyone! Sorry for the large delay, I'm doing this in my > free time, which is not that abundant. In this mail, I'm focusing only > on the largest change mentioned by Mark. I will answer the rest later. > > On Mon, Jul 08, 2019 at 10:36:14AM +0100, Marc Zyngier wrote: > > On 07/07/2019 14:22, Aleix Roca Nonell wrote: > > > This driver adds support for the RTD1296 and RTD1295 interrupt > > > controller (intc). It is based on both the BPI-SINOVOIP project and > > > Andreas Färber's previous attempt to submit a similar driver. > > > > > > There is currently no publicly available datasheet on this SoC and the > > > exact behaviour of the registers controlling the intc remain uncertain. > > > > > > This driver controls two intcs: "iso" and "misc". Each intc has its own > > > Interrupt Enable Register (IER) and Interrupt Status Resgister (ISR). > > > > Register > > > > > However, not all "misc" intc irqs have the same offsets for both ISR and > > > IER. For this reason an ISR to IER offsets table is defined. > > > > > > The driver catches the IER value to reduce accesses to the table inside the > > > interrupt handler. Actually, the driver stores the ISR offsets of currently > > > enabled interrupts in a variable. > > > > > > Signed-off-by: Aleix Roca Nonell > > > > I expect Andreas and you to sort the attribution issue. I'm certainly > > not going to take this in if things are unclear. > > > > > --- > > > drivers/irqchip/Makefile | 1 + > > > drivers/irqchip/irq-rtd129x.c | 371 ++++++++++++++++++++++++++++++++++ > > > 2 files changed, 372 insertions(+) > > > create mode 100644 drivers/irqchip/irq-rtd129x.c > > > > > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > > index 606a003a0000..0689c3956250 100644 > > > --- a/drivers/irqchip/Makefile > > > +++ b/drivers/irqchip/Makefile > > > @@ -100,3 +100,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o > > > obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o > > > obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o > > > obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o > > > +obj-$(CONFIG_ARCH_REALTEK) += irq-rtd129x.o > > > diff --git a/drivers/irqchip/irq-rtd129x.c b/drivers/irqchip/irq-rtd129x.c > > > new file mode 100644 > > > index 000000000000..76358ca50f10 > > > --- /dev/null > > > +++ b/drivers/irqchip/irq-rtd129x.c > > > @@ -0,0 +1,371 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#define RTD129X_INTC_NR_IRQS 32 > > > +#define DEV_NAME "RTD1296_INTC" > > > + > > > +/* > > > + * This interrupt controller (hereinafter intc) driver controls two intcs: "iso" > > > + * and "misc". Each intc has its own Interrupt Enable Register (IER) and > > > + * Interrupt Status Resgister (ISR). However, not all "misc" intc irqs have the > > > + * same offsets for both ISR and IER. For this reason an ISR to IER offsets > > > + * table is defined. Also, to reduce accesses to this table in the interrupt > > > + * handler, the driver stores the ISR offsets of currently enabled interrupts in > > > + * a variable. > > > + */ > > > + > > > +enum misc_int_en { > > > + MISC_INT_FAIL = 0xFF, > > > + MISC_INT_RVD = 0xFE, > > > + MISC_INT_EN_FAN = 29, > > > + MISC_INT_EN_I2C3 = 28, > > > + MISC_INT_EN_GSPI = 27, > > > + MISC_INT_EN_I2C2 = 26, > > > + MISC_INT_EN_SC0 = 24, > > > + MISC_INT_EN_LSADC1 = 22, > > > + MISC_INT_EN_LSADC0 = 21, > > > + MISC_INT_EN_GPIODA = 20, > > > + MISC_INT_EN_GPIOA = 19, > > > + MISC_INT_EN_I2C4 = 15, > > > + MISC_INT_EN_I2C5 = 14, > > > + MISC_INT_EN_RTC_DATA = 12, > > > + MISC_INT_EN_RTC_HOUR = 11, > > > + MISC_INT_EN_RTC_MIN = 10, > > > + MISC_INT_EN_UR2 = 7, > > > + MISC_INT_EN_UR2_TO = 6, > > > + MISC_INT_EN_UR1_TO = 5, > > > + MISC_INT_EN_UR1 = 3, > > > +}; > > > + > > > +enum iso_int_en { > > > + ISO_INT_FAIL = 0xFF, > > > + ISO_INT_RVD = 0xFE, > > > + ISO_INT_EN_I2C1_REQ = 31, > > > + ISO_INT_EN_GPHY_AV = 30, > > > + ISO_INT_EN_GPHY_DV = 29, > > > + ISO_INT_EN_GPIODA = 20, > > > + ISO_INT_EN_GPIOA = 19, > > > + ISO_INT_EN_RTC_ALARM = 13, > > > + ISO_INT_EN_RTC_HSEC = 12, > > > + ISO_INT_EN_I2C1 = 11, > > > + ISO_INT_EN_I2C0 = 8, > > > + ISO_INT_EN_IRDA = 5, > > > + ISO_INT_EN_UR0 = 2, > > > +}; > > > + > > > +unsigned char rtd129x_intc_enable_map_misc[RTD129X_INTC_NR_IRQS] = { > > > + MISC_INT_FAIL, /* Bit0 */ > > > + MISC_INT_FAIL, /* Bit1 */ > > > + MISC_INT_RVD, /* Bit2 */ > > > + MISC_INT_EN_UR1, /* Bit3 */ > > > + MISC_INT_FAIL, /* Bit4 */ > > > + MISC_INT_EN_UR1_TO, /* Bit5 */ > > > + MISC_INT_RVD, /* Bit6 */ > > > + MISC_INT_RVD, /* Bit7 */ > > > + MISC_INT_EN_UR2, /* Bit8 */ > > > + MISC_INT_RVD, /* Bit9 */ > > > + MISC_INT_EN_RTC_MIN, /* Bit10 */ > > > + MISC_INT_EN_RTC_HOUR, /* Bit11 */ > > > + MISC_INT_EN_RTC_DATA, /* Bit12 */ > > > + MISC_INT_EN_UR2_TO, /* Bit13 */ > > > + MISC_INT_EN_I2C5, /* Bit14 */ > > > + MISC_INT_EN_I2C4, /* Bit15 */ > > > + MISC_INT_FAIL, /* Bit16 */ > > > + MISC_INT_FAIL, /* Bit17 */ > > > + MISC_INT_FAIL, /* Bit18 */ > > > + MISC_INT_EN_GPIOA, /* Bit19 */ > > > + MISC_INT_EN_GPIODA, /* Bit20 */ > > > + MISC_INT_EN_LSADC0, /* Bit21 */ > > > + MISC_INT_EN_LSADC1, /* Bit22 */ > > > + MISC_INT_EN_I2C3, /* Bit23 */ > > > + MISC_INT_EN_SC0, /* Bit24 */ > > > + MISC_INT_FAIL, /* Bit25 */ > > > + MISC_INT_EN_I2C2, /* Bit26 */ > > > + MISC_INT_EN_GSPI, /* Bit27 */ > > > + MISC_INT_FAIL, /* Bit28 */ > > > + MISC_INT_EN_FAN, /* Bit29 */ > > > + MISC_INT_FAIL, /* Bit30 */ > > > + MISC_INT_FAIL /* Bit31 */ > > > +}; > > > + > > > +unsigned char rtd129x_intc_enable_map_iso[RTD129X_INTC_NR_IRQS] = { > > > + ISO_INT_FAIL, /* Bit0 */ > > > + ISO_INT_RVD, /* Bit1 */ > > > + ISO_INT_EN_UR0, /* Bit2 */ > > > + ISO_INT_FAIL, /* Bit3 */ > > > + ISO_INT_FAIL, /* Bit4 */ > > > + ISO_INT_EN_IRDA, /* Bit5 */ > > > + ISO_INT_FAIL, /* Bit6 */ > > > + ISO_INT_RVD, /* Bit7 */ > > > + ISO_INT_EN_I2C0, /* Bit8 */ > > > + ISO_INT_RVD, /* Bit9 */ > > > + ISO_INT_FAIL, /* Bit10 */ > > > + ISO_INT_EN_I2C1, /* Bit11 */ > > > + ISO_INT_EN_RTC_HSEC, /* Bit12 */ > > > + ISO_INT_EN_RTC_ALARM, /* Bit13 */ > > > + ISO_INT_FAIL, /* Bit14 */ > > > + ISO_INT_FAIL, /* Bit15 */ > > > + ISO_INT_FAIL, /* Bit16 */ > > > + ISO_INT_FAIL, /* Bit17 */ > > > + ISO_INT_FAIL, /* Bit18 */ > > > + ISO_INT_EN_GPIOA, /* Bit19 */ > > > + ISO_INT_EN_GPIODA, /* Bit20 */ > > > + ISO_INT_RVD, /* Bit21 */ > > > + ISO_INT_RVD, /* Bit22 */ > > > + ISO_INT_RVD, /* Bit23 */ > > > + ISO_INT_RVD, /* Bit24 */ > > > + ISO_INT_FAIL, /* Bit25 */ > > > + ISO_INT_FAIL, /* Bit26 */ > > > + ISO_INT_FAIL, /* Bit27 */ > > > + ISO_INT_FAIL, /* Bit28 */ > > > + ISO_INT_EN_GPHY_DV, /* Bit29 */ > > > + ISO_INT_EN_GPHY_AV, /* Bit30 */ > > > + ISO_INT_EN_I2C1_REQ /* Bit31 */ > > > +}; > > > + > > > +struct rtd129x_intc_data { > > > + void __iomem *unmask; > > > + void __iomem *isr; > > > + void __iomem *ier; > > > + u32 ier_cached; > > > + u32 isr_en; > > > + raw_spinlock_t lock; > > > + unsigned int parent_irq; > > > + const unsigned char *en_map; > > > +}; > > > + > > > +static struct irq_domain *rtd129x_intc_domain; > > > + > > > +static void rtd129x_intc_irq_handle(struct irq_desc *desc) > > > +{ > > > + struct rtd129x_intc_data *priv = irq_desc_get_handler_data(desc); > > > + struct irq_chip *chip = irq_desc_get_chip(desc); > > > + unsigned int local_irq; > > > + u32 status; > > > + int i; > > > + > > > + chained_irq_enter(chip, desc); > > > + > > > + raw_spin_lock(&priv->lock); > > > + status = readl_relaxed(priv->isr); > > > + status &= priv->isr_en; > > > + raw_spin_unlock(&priv->lock); > > > > What is this lock protecting? isr_en? > > > > > + > > > + while (status) { > > > + i = __ffs(status); > > > + status &= ~BIT(i); > > > + > > > + local_irq = irq_find_mapping(rtd129x_intc_domain, i); > > > + if (likely(local_irq)) { > > > + if (!generic_handle_irq(local_irq)) > > > + writel_relaxed(BIT(i), priv->isr); > > > > What are the write semantics of the ISR register? Hot bit clear? How > > does it work since mask() does the same thing? Clearly, something is > > wrong here. > > Sorry but I have not been able to found the definition of "hot bit > clear", could you explain it? Anyways, you were right, apparently the > mask/unmask code were doing nothing useful. More on this below. A hot-bit clear (or set) is a register where to write the bits that you want to clear (or set), leaving alone the bits that are written as zero. For example: REG = 0xFFFF clear_reg(0x1001) REG = 0x7FFE set_reg(0x1000) REG = 0xFFFE It is extremely useful for registers that need to be accessed concurrently (the GIC uses that a lot, for example). > > > > > > + } else { > > > + handle_bad_irq(desc); > > > + } > > > + } > > > + > > > + chained_irq_exit(chip, desc); > > > +} > > > + > > > +static void rtd129x_intc_mask(struct irq_data *data) > > > +{ > > > + struct rtd129x_intc_data *priv = irq_data_get_irq_chip_data(data); > > > + > > > + writel_relaxed(BIT(data->hwirq), priv->isr); > > > +} > > > + > > > +static void rtd129x_intc_unmask(struct irq_data *data) > > > +{ > > > + struct rtd129x_intc_data *priv = irq_data_get_irq_chip_data(data); > > > + > > > + writel_relaxed(BIT(data->hwirq), priv->unmask); > > > > What effect does this have on the isr register? The whole mask/unmask > > thing seems to be pretty dodgy... > > > > > +} > > > + > > > +static void rtd129x_intc_enable(struct irq_data *data) > > > +{ > > > + struct rtd129x_intc_data *priv = irq_data_get_irq_chip_data(data); > > > + unsigned long flags; > > > + u8 en_offset; > > > + > > > + en_offset = priv->en_map[data->hwirq]; > > > + > > > + if ((en_offset != MISC_INT_RVD) && (en_offset != MISC_INT_FAIL)) { > > > + raw_spin_lock_irqsave(&priv->lock, flags); > > > + > > > + priv->isr_en |= BIT(data->hwirq); > > > + priv->ier_cached |= BIT(en_offset); > > > + writel_relaxed(priv->ier_cached, priv->ier); > > > + > > > + raw_spin_unlock_irqrestore(&priv->lock, flags); > > > + } else if (en_offset == MISC_INT_FAIL) { > > > + pr_err("[%s] Enable irq(%lu) failed\n", DEV_NAME, data->hwirq); > > > + } > > > +} > > > + > > > +static void rtd129x_intc_disable(struct irq_data *data) > > > +{ > > > + struct rtd129x_intc_data *priv = irq_data_get_irq_chip_data(data); > > > + unsigned long flags; > > > + u8 en_offset; > > > + > > > + en_offset = priv->en_map[data->hwirq]; > > > + > > > + if ((en_offset != MISC_INT_RVD) && (en_offset != MISC_INT_FAIL)) { > > > + raw_spin_lock_irqsave(&priv->lock, flags); > > > + > > > + priv->isr_en &= ~BIT(data->hwirq); > > > + priv->ier_cached &= ~BIT(en_offset); > > > + writel_relaxed(priv->ier_cached, priv->ier); > > > + > > > + raw_spin_unlock_irqrestore(&priv->lock, flags); > > > + } else if (en_offset == MISC_INT_FAIL) { > > > + pr_err("[%s] Disable irq(%lu) failed\n", DEV_NAME, data->hwirq); > > > + } > > > +} > > > > So here's a thought: Why do we need all of this? If mask/unmask do their > > job correctly, we could just enable all interrupts in one go (just a > > 32bit write) at probe time, and leave all interrupts masked until they > > are in use. You could then drop all these silly tables that don't bring > > much... > > The idea of dropping all those tables look really good to me, that > would greatly simplify the code! I have been trying to mask all > interrupts on the probe function using the ISR register but while > doing so, I realized that it does not work. Writing to ISR does not > mask interrupts, apparently it only acknowledges them once they have > been triggered. On the scarse available documentation of this Soc I > cannot find a mask-like register. It seems interrupts are managed with > an ISR and an IER register. So it should be posible to use the enable > register to maks/unmask instead. These do work. However, that would > mean that we have to keep those ugly tables. > > Nonetheless we might still be able to do something else. Please, > correct me if I'm wrong, but do we really need to mask/unamsk in this > scenario? This is the devised board layout: > > +------+ +----------+ +---------+ > | | | | | | > | UART |-------|2 INTC |-------|c GIC | > | | +----|1 | +----|b | > +------+ | +--|0 | | +--|a | > | | | | | | | | > | | +----------+ | | +---------+ > | | > > Once the UART generates an interrupt it passes through the line 2 of > the custom realtek interrupt contoller before reaching the GIC's line > "c". On the INTC interrupt handler, we call chained_irq_enter/exit > to mask/unmask the GIC's "c" line. Because all of this realtek INTC > interrupt lines (2,1,0,...) are muxed on the GIC's line "c", this > means that while on the INTC interrupt handler it is not possible to > send further interrupts on the CPU. Given that interrupts are masked > on the GIC, it seems safe to just remove INTC's mask/unmask functions. No, that's not true. If you cannot mask an individual interrupt at the INTC level, it means that the only way to stop a screaming interrupt (because the endpoint has crashed or that the kernel doesn't have a driver for it) is to disable the interrupt at the GIC level, killing all users of the INTC. Also, because the core code doesn't really know that the INTC is behind the GIC, it cannot do that automatically. So if you get into that situation, your system is dead. Believe it or not, that's not something I want to see. An irqchip driver without a mask callback is a lose grenade, and the pin is in your pocket. > Therefore, the only work that this INTC handler would needs to do is > to acknowledge the interrupt by writing to the ISR, which it could be > done in the respective irq_ack callback of struct irq_chip instead of > in the handler body. > > I have implemented this solution and it seems to work. What do you > think? I'm missing something crucial? See above. Your system is terribly unsafe. Now, I'm pretty sure the Realtek folks could help you there. Or you could start trying to reverse engineer the thing, which shouldn't really hard (try poking at the registers next to the ones you already have). Thanks, M. -- Jazz is not dead, it just smells funny.