Re: Aliasing in pgtable-bits.h (CONFIG_64BIT_PHYS_ADDR)

[Juan Quintela <quintela@mandrakesoft.com>]

>>>>> "hartvig" == Hartvig Ekner <hartvig@ekner.info> writes:

hartvig> From pgtable-bits.h:
hartvig> #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)

hartvig> #define _PAGE_PRESENT               (1<<6)  /* implemented in software
hartvig> */
hartvig> #define _PAGE_READ                  (1<<7)  /* implemented in software
hartvig> */
hartvig> #define _PAGE_WRITE                 (1<<8)  /* implemented in software
hartvig> */
hartvig> #define _PAGE_ACCESSED              (1<<9)  /* implemented in software
hartvig> */
hartvig> #define _PAGE_MODIFIED              (1<<10) /* implemented in software
hartvig> */

hartvig> #define  _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug
hartvig> */
hartvig> #define _PAGE_GLOBAL                (1<<0)

hartvig> Is  the aliasing between R4KBUG & GLOBAL intentional? This is the only
hartvig> CONFIG case where it
hartvig> is  done. Superficially, I can't see R4KBUG used anywhere, so maybe it
hartvig> doesn't matter. But
hartvig> if R4KBUG truly isn't used, why not consider removing it entirely from
hartvig> all PTE layouts?

I will bet that this is related to the comment in
arch/mips/mm/tlb-r4k.c workaround that is unimplemented:

/* We will need multiple versions of update_mmu_cache(), one that just
 * updates the TLB with the new pte(s), and another which also checks
 * for the R4k "end of page" hardware bug and does the needy.
 */

Anyways, it appears that affected CPUS are only r4k and r4400 or so,
no big deal for rest of CPU's.

Later, Juan.

-- 
In theory, practice and theory are the same, but in practice they 
are different -- Larry McVoy