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[87.176.190.86]) by smtp.gmail.com with ESMTPSA id d13-20020a5d4f8d000000b0020c5253d911sm696888wru.93.2022.05.10.23.06.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 May 2022 23:06:42 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------HvU0i1DinKmp5ghfEeWOTFWm" Message-ID: <8695802e-6835-a717-c0ee-83b76d8a8875@gmail.com> Date: Wed, 11 May 2022 08:06:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 2/3] drm/amdgpu: add AMDGPU_VM_NOALLOC Content-Language: en-US To: =?UTF-8?B?TWFyZWsgT2zFocOhaw==?= References: <20220506112312.347519-1-christian.koenig@amd.com> <20220506112312.347519-2-christian.koenig@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: amd-gfx mailing list Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This is a multi-part message in MIME format. --------------HvU0i1DinKmp5ghfEeWOTFWm Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Mhm, it doesn't really bypass MALL. It just doesn't allocate any MALL entries on write. How about AMDGPU_VM_PAGE_NO_MALL ? Christian. Am 10.05.22 um 23:21 schrieb Marek Olšák: > A better name would be: > AMDGPU_VM_PAGE_BYPASS_MALL > > Marek > > On Fri, May 6, 2022 at 7:23 AM Christian König > wrote: > > Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL > allocation. > > Only compile tested! > > Signed-off-by: Christian König > --- >  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++ >  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  | 3 +++ >  drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c  | 3 +++ >  include/uapi/drm/amdgpu_drm.h           | 2 ++ >  4 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > index bf97d8f07f57..d8129626581f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c > @@ -650,6 +650,8 @@ uint64_t amdgpu_gem_va_map_flags(struct > amdgpu_device *adev, uint32_t flags) >                 pte_flag |= AMDGPU_PTE_WRITEABLE; >         if (flags & AMDGPU_VM_PAGE_PRT) >                 pte_flag |= AMDGPU_PTE_PRT; > +       if (flags & AMDGPU_VM_PAGE_NOALLOC) > +               pte_flag |= AMDGPU_PTE_NOALLOC; > >         if (adev->gmc.gmc_funcs->map_mtype) >                 pte_flag |= amdgpu_gmc_map_mtype(adev, > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > index b8c79789e1e4..9077dfccaf3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > @@ -613,6 +613,9 @@ static void gmc_v10_0_get_vm_pte(struct > amdgpu_device *adev, >         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; >         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); > > +       *flags &= ~AMDGPU_PTE_NOALLOC; > +       *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); > + >         if (mapping->flags & AMDGPU_PTE_PRT) { >                 *flags |= AMDGPU_PTE_PRT; >                 *flags |= AMDGPU_PTE_SNOOPED; > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > index 8d733eeac556..32ee56adb602 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c > @@ -508,6 +508,9 @@ static void gmc_v11_0_get_vm_pte(struct > amdgpu_device *adev, >         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; >         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); > > +       *flags &= ~AMDGPU_PTE_NOALLOC; > +       *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); > + >         if (mapping->flags & AMDGPU_PTE_PRT) { >                 *flags |= AMDGPU_PTE_PRT; >                 *flags |= AMDGPU_PTE_SNOOPED; > diff --git a/include/uapi/drm/amdgpu_drm.h > b/include/uapi/drm/amdgpu_drm.h > index 57b9d8f0133a..9d71d6330687 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -533,6 +533,8 @@ struct drm_amdgpu_gem_op { >  #define AMDGPU_VM_MTYPE_UC             (4 << 5) >  /* Use Read Write MTYPE instead of default MTYPE */ >  #define AMDGPU_VM_MTYPE_RW             (5 << 5) > +/* don't allocate MALL */ > +#define AMDGPU_VM_PAGE_NOALLOC         (1 << 9) > >  struct drm_amdgpu_gem_va { >         /** GEM object handle */ > -- > 2.25.1 > --------------HvU0i1DinKmp5ghfEeWOTFWm Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit Mhm, it doesn't really bypass MALL. It just doesn't allocate any MALL entries on write.

How about AMDGPU_VM_PAGE_NO_MALL ?

Christian.

Am 10.05.22 um 23:21 schrieb Marek Olšák:
A better name would be:
AMDGPU_VM_PAGE_BYPASS_MALL

Marek

On Fri, May 6, 2022 at 7:23 AM Christian König <ckoenig.leichtzumerken@gmail.com> wrote:
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation.

Only compile tested!

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  | 3 +++
 drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c  | 3 +++
 include/uapi/drm/amdgpu_drm.h           | 2 ++
 4 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index bf97d8f07f57..d8129626581f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -650,6 +650,8 @@ uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
                pte_flag |= AMDGPU_PTE_WRITEABLE;
        if (flags & AMDGPU_VM_PAGE_PRT)
                pte_flag |= AMDGPU_PTE_PRT;
+       if (flags & AMDGPU_VM_PAGE_NOALLOC)
+               pte_flag |= AMDGPU_PTE_NOALLOC;

        if (adev->gmc.gmc_funcs->map_mtype)
                pte_flag |= amdgpu_gmc_map_mtype(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index b8c79789e1e4..9077dfccaf3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -613,6 +613,9 @@ static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
        *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
        *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);

+       *flags &= ~AMDGPU_PTE_NOALLOC;
+       *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
+
        if (mapping->flags & AMDGPU_PTE_PRT) {
                *flags |= AMDGPU_PTE_PRT;
                *flags |= AMDGPU_PTE_SNOOPED;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 8d733eeac556..32ee56adb602 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -508,6 +508,9 @@ static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev,
        *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
        *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);

+       *flags &= ~AMDGPU_PTE_NOALLOC;
+       *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
+
        if (mapping->flags & AMDGPU_PTE_PRT) {
                *flags |= AMDGPU_PTE_PRT;
                *flags |= AMDGPU_PTE_SNOOPED;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 57b9d8f0133a..9d71d6330687 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -533,6 +533,8 @@ struct drm_amdgpu_gem_op {
 #define AMDGPU_VM_MTYPE_UC             (4 << 5)
 /* Use Read Write MTYPE instead of default MTYPE */
 #define AMDGPU_VM_MTYPE_RW             (5 << 5)
+/* don't allocate MALL */
+#define AMDGPU_VM_PAGE_NOALLOC         (1 << 9)

 struct drm_amdgpu_gem_va {
        /** GEM object handle */
--
2.25.1


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