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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?sje22o6nWEZLgj6GW+Uq37lQVmcV+x+YLQtDS/agDb3OfEg/ObYh0S0fo2LB?= =?us-ascii?Q?whj/pDQzuzZJJ4Wr7toSh/3rV4vf+IKBd4k82OpbUZQhP+jhKhKzKlIeVTNP?= =?us-ascii?Q?mHvsKzPTfCMjZdOtcoCof1LhncG4AA3Yo8m2xYNAEL/Q9AYoVPt9GmfdwR6O?= =?us-ascii?Q?Ls7YhYlhMuxV7mz3ccRRGcpGvOzBMgKDs3HTEEAUEG1cNDH0UOUw9W/uFk12?= =?us-ascii?Q?/E2Mxks9ffAX/IhiVc327BqqW51YXgD1DHlmKMXLKMvQC3G7ZmyVfnl++r7b?= =?us-ascii?Q?oRSlvNbYVkMMFgWmBGKTLNl1ksdFsDYU9K2wb3ziuKoPI6l8+yiw9Z29NJ60?= =?us-ascii?Q?LY4c+KraOpFjsOQcRrz4jcDBcJwXuyT8ZdTxoA92e4nNpaejSOytj/57Rn0I?= =?us-ascii?Q?KIod/CFOO636hq1jjlKGGYLIpwz0fW1NTBmI0VpslGh1R70rshFzt9RCVcnI?= =?us-ascii?Q?/1TXgWoddp3R1S7hw3A1D0CSv4BG2cUAt9Os955MhOgNMM+r4cFiCvdPe36z?= =?us-ascii?Q?kZpoCkYYcPfP3weKRUHwJisyLfSJbJ0QG/pVmY972ozc/IexkeX3NkDn/20z?= =?us-ascii?Q?VuhWOBb/kQRMaePLq6NRDG9CWKMIELQdVOUWiLMTVPQGgesJQtMj+jCEstQl?= =?us-ascii?Q?AUPW4Q5+qz0eE/9Ck6DzMZ4YMatFzz8fCUQqjHWL9yl6U0SzoBGuJTI56+6B?= =?us-ascii?Q?PLgquOYcq5lGZm5wblAK9T91/Z4W/d+BXijW6q3yjVL5c5ePC0kSLlaaguHm?= =?us-ascii?Q?zuUZSMsOZoWWXhMyuKDHXxVPb/XuLrxOo2K8gHXPjYCq7LF7evVwmYGHfwN3?= =?us-ascii?Q?Lk5Z/xKfKuF8TqQoLuyOYrHBO2lE3MrSMeSbG0icJPitF4yYr+6Ae4pWnvnh?= =?us-ascii?Q?gMxa/UeuMnVv3Dy9ZkohyLoOoDaWlYdsBuzqFj2ycOjttL3onSlBc1WLwYjx?= =?us-ascii?Q?XVAX18Yje7WujrJsVuu3McYya1w6M0VuExhrT7q4Vzs4e7AMYMjEcXl8yQG8?= =?us-ascii?Q?wu7RIiBrHg1HeXumryeeP0qqnkZIka1XWsh/CRd7NJaZkSlo/pYmo2h7cyUY?= =?us-ascii?Q?D11HxpBYIvtBmjdpvCAEw9XH+JS7BZ9nw5rf4Oea4Thnnutu9a6BnGwOdsYX?= =?us-ascii?Q?msYyj2N2H6dVgA9Pg+0Rv5jjXZGWfYfgdk0wiuJDkjXY+EEqEB5xUsmZKM6L?= =?us-ascii?Q?BjfM8gvYXHmhLQ+NUDiLlBcGnde9jgJeCjm9c8ygC1tMF3F5kYGfiw7ZtnI/?= =?us-ascii?Q?0LEdGEYjCrWOlqGPTUythsZE2HmVVDb0NI37AwxH6/skWt+HwLYypECx9SCF?= =?us-ascii?Q?v4vJtneIobngfN4IreNaapvFnoZgS30IgkLEapsSGRtYfl98uh5URXDI9m0j?= =?us-ascii?Q?D/avOFkzCG6/bRq2f7rhzukApwE5oJhQR3HiOi5QKiDTtddX4cxCVrzCNkEh?= =?us-ascii?Q?xvJ9l7Z0WbtpDP0nXGedzfsWD5N+DPZfCAyZrtTQHNET6f3M3D1GMvGBO9gm?= =?us-ascii?Q?Gh7IeIXJ+vfV74AgBPFQhBqdXyChJUbiyyg4v+Gl5LtQHDoX9oAFTECqmKZW?= =?us-ascii?Q?rl+LfqYIFE6QN/Huc4iQmpSHYlbHjNKdSGQ71g48t4aYjFpFoaqtkVRHSLOp?= =?us-ascii?Q?8ZUNWc1kStAAaQc0nhfNBPk=3D?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: cfa1e48e-20c3-48a7-9863-08dd88c365ad X-MS-Exchange-CrossTenant-AuthSource: LV2PR01MB7792.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2025 15:18:16.5328 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tQuboGMWRt1Ro5EIyuyjk+Vm13/fDwd3ACG0e1htxh2B8Qaa3cCf1FYKSCdjz/phUuz249zysDlxzqAF9aNNB+GW3k1mYF7dLCQO0PmYh+Ir2WjQtbqholtdw/XPbNl6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR01MB6212 Marc Zyngier writes: > On Fri, 25 Apr 2025 03:47:41 +0100, > D Scott Phillips wrote: >> >> Updates to HCR_EL2 can rarely corrupt simultaneous translations for data >> addresses initiated by load/store instructions. Only instruction >> initiated translations are vulnerable, not translations from prefetches >> for example. A DSB before the store to HCR_EL2 is sufficient to prevent older >> instructions from hitting the window for corruption, and an ISB after >> is sufficient to prevent younger instructions from hitting the window >> for corruption. >> >> Signed-off-by: D Scott Phillips >> --- >> v1: https://lore.kernel.org/kvmarm/20250415154711.1698544-2-scott@os.amperecomputing.com/ >> Changes since v1: >> - Add a write_sysreg_hcr() helper (Oliver) >> - Add more specific wording in the errata description (Oliver & Marc) >> >> arch/arm64/Kconfig | 17 +++++++++++++++++ >> arch/arm64/include/asm/hardirq.h | 4 ++-- >> arch/arm64/include/asm/sysreg.h | 10 ++++++++++ >> arch/arm64/kernel/cpu_errata.c | 14 ++++++++++++++ >> arch/arm64/kvm/at.c | 8 ++++---- >> arch/arm64/kvm/hyp/include/hyp/switch.h | 2 +- >> arch/arm64/kvm/hyp/nvhe/mem_protect.c | 2 +- >> arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- >> arch/arm64/kvm/hyp/vhe/switch.c | 2 +- >> arch/arm64/kvm/hyp/vhe/tlb.c | 4 ++-- >> arch/arm64/tools/cpucaps | 1 + >> 11 files changed, 54 insertions(+), 12 deletions(-) >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index a182295e6f08b..3ae4e80e3002b 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -464,6 +464,23 @@ config AMPERE_ERRATUM_AC03_CPU_38 >> >> If unsure, say Y. >> >> +config AMPERE_ERRATUM_AC04_CPU_23 >> + bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." >> + default y >> + help >> + This option adds an alternative code sequence to work around Ampere >> + errata AC04_CPU_23 on AmpereOne. >> + >> + Updates to HCR_EL2 can rarely corrupt simultaneous translations for >> + data addresses initiated by load/store instructions. Only >> + instruction initiated translations are vulnerable, not translations >> + from prefetches for example. A DSB before the store to HCR_EL2 is >> + sufficient to prevent older instructions from hitting the window >> + for corruption, and an ISB after is sufficient to prevent younger >> + instructions from hitting the window for corruption. >> + >> + If unsure, say Y. >> + >> config ARM64_WORKAROUND_CLEAN_CACHE >> bool >> >> diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h >> index cbfa7b6f2e098..77d6b8c63d4e6 100644 >> --- a/arch/arm64/include/asm/hardirq.h >> +++ b/arch/arm64/include/asm/hardirq.h >> @@ -41,7 +41,7 @@ do { \ >> \ >> ___hcr = read_sysreg(hcr_el2); \ >> if (!(___hcr & HCR_TGE)) { \ >> - write_sysreg(___hcr | HCR_TGE, hcr_el2); \ >> + write_sysreg_hcr(___hcr | HCR_TGE); \ >> isb(); \ >> } \ >> /* \ >> @@ -82,7 +82,7 @@ do { \ >> */ \ >> barrier(); \ >> if (!___ctx->cnt && !(___hcr & HCR_TGE)) \ >> - write_sysreg(___hcr, hcr_el2); \ >> + write_sysreg_hcr(___hcr); \ >> } while (0) >> >> static inline void ack_bad_irq(unsigned int irq) >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 2639d3633073d..d41eeba7f8201 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -1185,6 +1185,16 @@ >> write_sysreg_s(__scs_new, sysreg); \ >> } while (0) >> >> +#define write_sysreg_hcr(__val) do { \ >> + if(IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \ >> + alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23)) \ >> + asm volatile("dsb nsh; msr hcr_el2, %x0; isb" \ >> + : : "rZ" (__val)); \ >> + else \ >> + asm volatile("msr hcr_el2, %x0" \ >> + : : "rZ" (__val)); \ >> +} while (0) >> + > > I'm worried that some of these accesses may occur before we compute > the capabilities. I'd be more confident if the default was to have the > workaround, and only to relax it once we know we're not on a broken > system. OK, will do > But that leaves the question of the early stuff that runs before we > get to C code. Are you sure this isn't affected by this issue (for > example, the code in head.S, hyp-stub.S, and el2-setup.h)? Ya, that's a good point. The corrupted translations can happen speculatively, so there's every reason to think all those places also need to be considered. I'll take a look everywhere now, not just at C. >> #define read_sysreg_par() ({ \ >> u64 par; \ >> asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index b55f5f7057502..60f1b70fc0845 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -557,6 +557,13 @@ static const struct midr_range erratum_ac03_cpu_38_list[] = { >> }; >> #endif >> >> +#ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 >> +static const struct midr_range erratum_ac04_cpu_23_list[] = { >> + MIDR_ALL_VERSIONS(MIDR_AMPERE1A), >> + {}, >> +}; >> +#endif >> + >> const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE >> { >> @@ -875,6 +882,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38, >> ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list), >> }, >> +#endif >> +#ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 >> + { >> + .desc = "AmpereOne erratum AC04_CPU_23", >> + .capability = ARM64_WORKAROUND_AMPERE_AC04_CPU_23, >> + ERRATA_MIDR_RANGE_LIST(erratum_ac04_cpu_23_list), >> + }, >> #endif > > This needs to be captured in Documentation/arch/arm64/silicon-errata.rst. OK, will do, thanks Marc.