From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DEC53BE635; Fri, 31 Jul 2026 14:17:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785507446; cv=none; b=lEkJ06yUeR/k8aXVy61HK03531r88OG56BiCW/f5XC69MV3Mj45U56f/FVYzkR6MfXJbd5oHMYVjQNH4StAlexYr0SiilKhMHYaSfmhnuxHPR1G8PNMNJ8YsAW48vKeUbfAqNCf01r66V/+4RuGNXuFeR/05Ah4D17fGWgAYclg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785507446; c=relaxed/simple; bh=ny+WAyjL0ZdwMfSRACQxN0SP59/++2QN+UQ1u5iB7aQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=iQUuIqBD7S5y+Sm9V1Nkaw+C/A2M5QMkQ8HY3Cd85k8F3+HnKzCGJ7LSGaGAqD3TbKec0jCG1MAP1wqJIaa7J6jYQTSHPzikNfngoSfZ4e9x3uFLo/118kwd6JS+frS8EAL8LYEDoRb6sLoaCY+8+v/y3I5En4Mv2uNaiZE4SeE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fOSctRSm; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fOSctRSm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C6CE51F000E9; Fri, 31 Jul 2026 14:17:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785507444; bh=U0aoTx+JIMbNcemvR5BXn3jXNyYGeWb89EHxZLv8ff0=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=fOSctRSm8cIqWDiHJFYiZMeOidcwD4vGG1KQbnwRXNBXPFblLD/B5Te+bDb1jTWlC F1h/Iq5qStKIgccVUO6RZGvMLaW/YwGl50eIaL6dzcGhQMnIb79YTBdKPElyAKmvRf h1IvWndxICYUV8mvilnpBD4mDnkC/da4gcNK9L4NWEKsUT0z+80pVvUEu0H8u0kfr5 0X/uf6c+tfppW7efvGwd5J+GWTeEl1cRhKDx/UureKjvPeTzJK+u4XmSIEFtFIqnuf uB7Uu1lvEmvDzQIBW1x1GQPq7MBnGgGWrt7yNpY6cZ+p90H2CRPzVjcnS7f+x2ZadP GELFhp6Kjfu8g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wpo38-0000000Ay4o-0kT9; Fri, 31 Jul 2026 14:17:22 +0000 Date: Fri, 31 Jul 2026 15:17:21 +0100 Message-ID: <86bjbnckge.wl-maz@kernel.org> From: Marc Zyngier To: Steffen Eiden Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: Re: [PATCH v5 06/31] arm64/sysreg: Convert SPSR_ELx to automatic register generation In-Reply-To: <20260731130902.654679-7-seiden@linux.ibm.com> References: <20260731130902.654679-1-seiden@linux.ibm.com> <20260731130902.654679-7-seiden@linux.ibm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-s390@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: seiden@linux.ibm.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, agordeev@linux.ibm.com, gra@linux.ibm.com, arnd@arndb.de, catalin.marinas@arm.com, borntraeger@linux.ibm.com, imbrenda@linux.ibm.com, david@kernel.org, fritz@linux.ibm.com, tabba@google.com, ggala@linux.ibm.com, hari55@linux.ibm.com, hca@linux.ibm.com, brueckner@linux.ibm.com, iii@linux.ibm.com, frankja@linux.ibm.com, joey.gouly@arm.com, nrb@linux.ibm.com, oss@nina.schoetterlglausch.eu, oupton@kernel.org, pbonzini@redhat.com, suzuki.poulose@arm.com, svens@linux.ibm.com, Ulrich.Weigand@de.ibm.com, gor@linux.ibm.com, will@kernel.org, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 31 Jul 2026 14:08:34 +0100, Steffen Eiden wrote: > > Convert SPSR_EL{1, 2, 12} to automatic register generation as per > DDIO616 2026-06. No functional change. > > Signed-off-by: Steffen Eiden > --- > arch/arm64/include/asm/sysreg.h | 3 -- > arch/arm64/tools/sysreg | 72 +++++++++++++++++++++++++++++++++ > 2 files changed, 72 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 4bfdac9401bd..1aa601c95188 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -295,7 +295,6 @@ > #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) > #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) > > -#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) > #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) > > #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) > @@ -518,7 +517,6 @@ > #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) > > #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > -#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) > #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0) > @@ -604,7 +602,6 @@ > #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) > #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) > #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) > -#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) > #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) > #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) > #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 7cb61aca3797..2a4b94e8c62f 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -401,6 +401,78 @@ Res0 3:1 > Field 0 SO > EndSysreg > > +Sysreg SPSR_EL1 3 0 4 0 0 > +Res0 63:37 > +Field 36 UNIJ > +Res0 35:34 > +Field 33 PPEND > +Res0 32 > +Field 31 N > +Field 30 Z > +Field 29 C > +Field 28 V > +Field 27 Q > +Field 26:25 IT01 > +Field 24 DIT > +Field 23 SSBS > +Field 22 PAN > +Field 21 SS > +Field 20 IL > +Field 19:16 GE > +Field 15:10 IT27 I'm sorry, but this is complete nonsense. It looks like you have lifted the AArch32 version of the definition, and not the AArch64 view (which really is what matters here). > +Field 9 E > +Field 8 A > +Field 7 I > +Field 6 F > +Field 5 T > +Field 4 M4 > +Enum 3:0 M I don't think you should split the M field as such. The AArch32 encoding uses bit 4, and should be described. > + 0b0000 EL0 > + 0b0100 EL1t > + 0b0101 EL1h > + 0b1000 EL1tnv > + 0b1001 EL1hnv Please do *not* invent names. These are EL2t/EL2h, and cannot be anything else. M. -- Without deviation from the norm, progress is not possible.