From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA1A6C4332F for ; Wed, 28 Dec 2022 11:14:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbiL1LOS (ORCPT ); Wed, 28 Dec 2022 06:14:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229708AbiL1LOR (ORCPT ); Wed, 28 Dec 2022 06:14:17 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45AC710FDA; Wed, 28 Dec 2022 03:14:16 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E8BA1B81639; Wed, 28 Dec 2022 11:14:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 867D4C433EF; Wed, 28 Dec 2022 11:14:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672226053; bh=xMjgukjtHzE0+lVwng5j2D0+boNEBOyC78JjAszKCE4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PKlHAant/Ojc+U94Px/F4pmlzcZKOOejI3Z4u1rOyLUglMo+T3SGxC6pfoiS+cNb3 o19ZWMA0nEx9XSAvZykv0FgpXFJUDsx+yJxEoUHYmvIbwQb9coeLdov5RfhSjbXPCa RfgqyTEwFGDiIR2eTd+701hfRriLPh9zsUYKOiZ58o3UXPbjuOZKxn4vfcMSaJycjk H/msAen1LqLfwW2jSXv9isCQUknemX5jhsDD6WePXc54pBm9VlkigxtsZn4na16NzU Y6l6pZwpPOuHAzdHGRwzORO/MUx57cILwWblh4jOy0fogxddjXrxbCQAopINrf25I7 Qmq4R5NauN1hw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pAUNv-00FXOu-87; Wed, 28 Dec 2022 11:14:11 +0000 Date: Wed, 28 Dec 2022 11:14:11 +0000 Message-ID: <86bknnbx18.wl-maz@kernel.org> From: Marc Zyngier To: Pavan Kondeti Cc: Yogesh Lal , , , Subject: Re: [PATCH] irqchip: gic-v3: Handle failure case of CPU enters low power state In-Reply-To: <20221227103638.GA3974604@hu-pkondeti-hyd.qualcomm.com> References: <1671734140-15935-1-git-send-email-quic_ylal@quicinc.com> <20221227103638.GA3974604@hu-pkondeti-hyd.qualcomm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: quic_pkondeti@quicinc.com, quic_ylal@quicinc.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, 27 Dec 2022 10:36:38 +0000, Pavan Kondeti wrote: > > Hi Yogesh, > > On Fri, Dec 23, 2022 at 12:05:40AM +0530, Yogesh Lal wrote: > > When CPU enter in low power mode it disable the redistributor and > > Group1 interrupts. And re-initialise the system registers on wakeup. > > > > But in case of failure to enter low power mode need to enable > > the redistributor and Group1 interrupts. > > > > Signed-off-by: Yogesh Lal > > --- > > drivers/irqchip/irq-gic-v3.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > index 997104d..4904f00 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -1376,7 +1376,7 @@ static int gic_retrigger(struct irq_data *data) > > static int gic_cpu_pm_notifier(struct notifier_block *self, > > unsigned long cmd, void *v) > > { > > - if (cmd == CPU_PM_EXIT) { > > + if (cmd == CPU_PM_EXIT || cmd == CPU_PM_ENTER_FAILED) { > > if (gic_dist_security_disabled()) > > gic_enable_redist(true); > > gic_cpu_sys_reg_init(); > > static int gic_cpu_pm_notifier(struct notifier_block *self, > unsigned long cmd, void *v) > { > if (cmd == CPU_PM_EXIT) { > if (gic_dist_security_disabled()) > gic_enable_redist(true); > gic_cpu_sys_reg_init(); > } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { > gic_write_grpen1(0); > gic_enable_redist(false); > } > return NOTIFY_OK; > } > > During CPU_PM_ENTER notification, we are not doing anything for the > !gic_dist_security_disabled() case. Since CPU_PM_ENTER_FAILED notification > arrive when CPU fails to power down, do we need to reinitialize the > system registers? IOW, should we do different handling for CPU_PM_ENTER_FAILED > based on gic_dist_security_disabled()? What does it gain you apart from the extra complexity? gic_cpu_sys_reg_init() does very little, and makes sure we're always back into a sane state. M. -- Without deviation from the norm, progress is not possible.