From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: Broken LVDS output at mode changes Date: Thu, 29 Mar 2012 08:07:05 -0700 Message-ID: <86d37vo38m.fsf@sumi.keithp.com> References: <20120329121638.GA20275@phenom.ffwll.local> <1333025081_141778@CP5-2952> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 679899E78C for ; Thu, 29 Mar 2012 08:07:12 -0700 (PDT) In-Reply-To: <1333025081_141778@CP5-2952> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , Daniel Vetter , Takashi Iwai Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org <#part sign=pgpmime> On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson wrote: > In conjunction with bits Power Sequence Progress field and Power Cycle > Delay Active, this bit set to a one indicates that the panel is > currently powered up or is currently in the power down sequence and it > is unsafe to change the timing, port, and DPLL registers for the pipe or > transcoder that is assigned to the panel output. The theory was that as we don't touch the DPLL and only modify the scaler, that the panel wouldn't care. I wonder what's confusing this one... -- keith.packard@intel.com