From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DB5F3346A6 for ; Tue, 4 Nov 2025 17:22:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762276957; cv=none; b=PccwfJCs/9uNWlpvldW0ygCjZUZXaV03+Laq7ZrjhLx5wp0Hau0JPEuQIUEOz+3hU8vhUi5D9vOgaFxi7BMwitT1xfidAhgverBCcUadrUA6KlpiSxCorYTwZ6GmCKYuTNzZkpQvUq5TbCULygcs5blJ9X3uB2odiM5LCU199qs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762276957; c=relaxed/simple; bh=iUZ3N3RHvseLx+CotbOn+5bZMf+u+c4VO9Kg+qOLrVA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=iKkc6//GPqHvdks4dWSKzCfXiTwe5gXXZ7qob7z0bF3A+n9sGsrmz9kzi4A25idF2XKYZz/s4I+qZr9TKZdTEKcJcfCzQNsNbTVzvL/S2InpL+zHl5Q/1/ab54WuKwFJLBTJPebpZZts2Bs4CUcIZiU8SIAXKid2W8NbBnZQ4EA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SfOW3hyL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SfOW3hyL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39F99C4CEF7; Tue, 4 Nov 2025 17:22:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762276957; bh=iUZ3N3RHvseLx+CotbOn+5bZMf+u+c4VO9Kg+qOLrVA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SfOW3hyLAuC+DmP6QnLsMcVsa4W8zvFii49QP6kZ6T0IW37/W0a9tr2yBoC/olCl+ fQvpdKsn5uA9bn4zeTkCXV1nrgx5VofgcGP0dY69jimF+hjKRvvDjMSvbnlHcMJv0Z mYQGUSZ7xvN+skE97lNcaFO9TS1ZoxGHR4fv7foWceAytGmfYzSL3Mc9FVBpatsbZQ 5EyYa2AwW9N6SoYq27syR1LwqMXCZWvSfraihWjibmbRWdoxLruqjnQKw7JF6AEydQ mzr8vdyeAwRxzijaddtW91G4mKwqBwYRRHxNBFrCuTsSmksKV1Pl0Du1ZmsiQ9mMMJ h6Gf9f7KT5pSQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vGKjr-00000002MrK-0GNT; Tue, 04 Nov 2025 17:22:35 +0000 Date: Tue, 04 Nov 2025 17:22:34 +0000 Message-ID: <86ecqdvhk5.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com Subject: Re: [PATCH v1 2/8] KVM: arm64: Trap access to ALLINT if FEAT_NMI not supported by the guest In-Reply-To: References: <20251104125906.1919426-1-tabba@google.com> <20251104125906.1919426-3-tabba@google.com> <86h5v9vnfc.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 04 Nov 2025 15:30:34 +0000, Fuad Tabba wrote: > > Hi Marc, > > On Tue, 4 Nov 2025 at 15:15, Marc Zyngier wrote: > > > > On Tue, 04 Nov 2025 12:59:00 +0000, > > Fuad Tabba wrote: > > > > > > Access to ALLINT is part of FEAT_NMI. If a guest does not support this > > > feature, any access to this register must be trapped to the hypervisor > > > (EL2). > > > > > > KVM didn't configure this trap, potentially allowing a guest to toggle > > > all interrupt mask when it doesn't support FEAT_NMI. Fix this by > > > checking if the guest has FEAT_NMI support. > > > > > > Signed-off-by: Fuad Tabba > > > --- > > > arch/arm64/include/asm/kvm_emulate.h | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > > > diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h > > > index 0f8311263edf..3fc62808c548 100644 > > > --- a/arch/arm64/include/asm/kvm_emulate.h > > > +++ b/arch/arm64/include/asm/kvm_emulate.h > > > @@ -688,6 +688,9 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) > > > else > > > vcpu->arch.hcrx_el2 |= HCRX_EL2_MCE2; > > > > > > + if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP)) > > > + vcpu->arch.hcrx_el2 |= HCRX_EL2_TALLINT; > > > + > > > if (kvm_has_tcr2(kvm)) > > > vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; > > > > > > > I think this is moving in the wrong direction. We have for quite some > > time now tried to automatically derive these behaviours from the guest > > config, as we do for FGUs. > > > > I would like to see a similar behaviour being introduced for non-FGT > > bits so that we don't have to worry about these things anymore. > > I agree that we should make this more like FGT, but since that will > likely require a bit more time (and probably a couple of respins), > should we fix the HCRX traps as they are now? I don't think this is fixing anything. Where does the trap go? There is no triaging, no handling. At the very least, this needs to be defined. Thanks, M. -- Without deviation from the norm, progress is not possible.