From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65DD2271273 for ; Tue, 25 Feb 2025 13:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740491655; cv=none; b=ttOitYY2DSXXBkhd/h2EKBYGIdWU5RVjQlKrliS4zkThOtlVG3zYzbtzP9H3PZtS/xSqhmSmSBUgTOpMTIvBnpI2/zsjvQrE5tkW/fCo+3ygFN+hPr2slDZEIxa9UBo8XIsUajDUE9AlC03YxU8Q2XhTwFXtTCpDVa4IVj87AHI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740491655; c=relaxed/simple; bh=sJBgf6JH/KGP3h5jphfCZqiK68MtmDr8IYCTk/ysiwg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=fYCUI5swFCSlbLyxkI9TAfn5jAQsanla2D5GfGsmNBeXgRtLUP3MoOpfhuKwEQMUDuV2VUvS2Un+8e7FdYGDXK0ltBYHpyQZANJkeDPFfWRXUa2DhplVm5zchPLo6Wrby9WQD0uil6NrCN9cd6qPJxEZ9b1EPpJ7QVpdNe18eB4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PXVVHd3V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PXVVHd3V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E20AAC4CEE6; Tue, 25 Feb 2025 13:54:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740491654; bh=sJBgf6JH/KGP3h5jphfCZqiK68MtmDr8IYCTk/ysiwg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PXVVHd3VAEPCaVnUa0Z1/sOww3WzxmVzcfTR/QsnCSApnvyKcXduFK5Jyyf+OqF+x 4u+RtSvshEx+m/oGOxRTkUO7TVQArYFx53RIXw5AfexzpvifFUr+j1KLI6rjniA4y6 TX+jhu6yVgNOp7ox3DZtdB5pIbw0iCVVFGYN2v7aElmQGo2hJTjEDhpkJPMpIUDHFg /BgOu+O54ulwwFlvzzfz0PcfKj2KT0sbmbNRH8SE7hzraNHh0wI28uWLlOwfQT0bOU YUD7S78TDhh3+fv4ojwV4xciWpOEyvx6cWUY1Jv5PPQ+BGsLoPwHGenqAC1fXdLRUV 0ulLb3exVH0Vw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tmvO0-007mfR-Rw; Tue, 25 Feb 2025 13:54:13 +0000 Date: Tue, 25 Feb 2025 13:54:12 +0000 Message-ID: <86eczmqge3.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Sebastian Ott Subject: Re: [PATCH v4 0/5] KVM: arm64: Writable MIDR/REVIDR (and associated baggage) In-Reply-To: <20250225005401.679536-1-oliver.upton@linux.dev> References: <20250225005401.679536-1-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, sebott@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 25 Feb 2025 00:53:56 +0000, Oliver Upton wrote: > > This is hopefully the last take on the writable MIDR/REVIDR/AIDR series. > > I've restructured things in order to work around the existing > shortcomings, have a stable-worthy backport for SMIDR_EL1, and avoid > breaking ABI. > > I personally hate using a capability for this, but given the subtlety of > the issue (and our habit of breaking save/restore) it is probably best > to put userspace in the driver's seat. > > v3: https://lore.kernel.org/kvmarm/20250218163443.32836-1-sebott@redhat.com/ > > v3 -> v4: > - Trap SMIDR_EL1 accesses so they actually UNDEF > - Snapshot MIDR, REVIDR, and AIDR from the boot CPU > - Require buy-in from userspace to make ID registers writable Here's what I added to the series in order to handle AIDR/REVIDR. Not exactly pretty, but it does the job (tested on my Synquacker running a hand-crafted guest). Feel free to squash it into patch #1. Thanks, M. From: Marc Zyngier Date: Tue, 25 Feb 2025 13:46:55 +0000 Subject: [PATCH] KVM: arm64: Map AArch32 AIDR/REVIDR to their AArch64 counterpart In order to handle AIDR/REVIDR traps from an AArch32 guest, add some ugly handling to kvm_handle_cp15_32(). Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c1727fe6c8cb0..1ceaec61796c9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4398,9 +4398,13 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) * Certain AArch32 ID registers are handled by rerouting to the AArch64 * system register table. Registers in the ID range where CRm=0 are * excluded from this scheme as they do not trivially map into AArch64 - * system register encodings. + * system register encodings, except for AIDR/REVIDR. */ - if (params.Op1 == 0 && params.CRn == 0 && params.CRm) + if (params.Op1 == 0 && params.CRn == 0 && + (params.CRm || params.Op2 == 6 /* REVIDR */)) + return kvm_emulate_cp15_id_reg(vcpu, ¶ms); + if (params.Op1 == 1 && params.CRn == 0 && + params.CRm == 0 && params.Op2 == 7 /* AIDR */) return kvm_emulate_cp15_id_reg(vcpu, ¶ms); return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs)); -- 2.39.2 -- Without deviation from the norm, progress is not possible.