From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A24199BC for ; Tue, 26 Nov 2024 16:30:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732638619; cv=none; b=TBVUH1+ig04tmpqd/ZeBNHB/OEHIK3kBdaaYuIfc3cKlOct/6WNzl77/k1x/U7bPEOViG43/kvSd05lH8+ktaMQIyOyIucAhxyTG9S/52CsO7MJ0eOEzip06FuTQDDKRhmH+CWJAfsdXtIr0rU58xxdogC3QixsIgZ6bK8OYS+o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732638619; c=relaxed/simple; bh=W2P9kBCA/lMEwgV3a21V/MPjCI6RTvlgYfJj6gZss+Q=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=HGFa7R5dI9T2BIEREZx14KXEM2obiDGkKjLcw/UhQv9XWP/yLlnvUhR1Ly05TX3AyC3Q8naMtrlgtbvp86Jek8ALh5QcAPmsBh2JBLOYPGc6swFPFr8cCz7E/mJhvZomYGgbcTjqNfqtFANj3T6bkEWi75xzt4qr0ngrEha5Cpw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UB4VxGAC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UB4VxGAC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 40A81C4CECF; Tue, 26 Nov 2024 16:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732638619; bh=W2P9kBCA/lMEwgV3a21V/MPjCI6RTvlgYfJj6gZss+Q=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=UB4VxGACdNmWv1C9hBpnKM9KJF8lwyGFXYPcQF+TzStnMhL//+Mfv1ecbZ2EQPw28 ZD+1CD7q62QjvY42xByD7cbsSvbR6nN1k2N7QrPX4WXlO1tSqG0JFgpqfFadMR+tUX tqzTLWhq+yVlP45mDXfosWTfGmG7HnkfOaCEntUJ9zAQSvW1UzB+pFCy7PxScvkQTp Y05Te3f1+iGsNF6DFR99gV8V6I9h1n7N1QaFUt+Qguai3AC1Xyk3x582I1VGW9kMOz DuLwiybhjUBMs59KLny8EkCohcml7zmGLSmEA5wg7PC617hxSrLtDFPonS91nzyjnq /1JjOQmHvWVGg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tFyS9-00G36n-2D; Tue, 26 Nov 2024 16:30:17 +0000 Date: Tue, 26 Nov 2024 16:30:16 +0000 Message-ID: <86ed2yufdz.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Alexandru Elisei Subject: Re: [PATCH] KVM: arm64: Fix S1/S2 combination when FWB==1 and S2 has Device memory type In-Reply-To: References: <20241125094756.609590-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, alexandru.elisei@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 26 Nov 2024 15:27:00 +0000, Oliver Upton wrote: > > On Mon, Nov 25, 2024 at 09:47:56AM +0000, Marc Zyngier wrote: > > The G.a revision of the ARM ARM had it pretty clear that HCR_EL2.FWB > > had no influence on "The way that stage 1 memory types and attributes > > are combined with stage 2 Device type and attributes." (D5.5.5). > > > > However, this wording was lost in further revisions of the architecture. > > > > Restore the intended behaviour, which is to take the strongest memory > > type of S1 and S2 in this case, as if FWB was 0. The specification is > > being fixed accordingly. > > Since you're already asking for a spec fix, could you mention that the > column headers in DDI0487K.a Table D8-95 are incorrect? MemAttr[1:0] is > used twice, although I believe the first column is actually MemAttr[3:2]. That one has already been fixed as D22366, as described in the Known Issues document for version K.a (issue 07) [1]. Thanks, M. [1] https://developer.arm.com/documentation/102105/latest/ -- Without deviation from the norm, progress is not possible.