From: Marc Zyngier <maz@kernel.org>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com,
will@kernel.org, anshuman.khandual@arm.com, mark.rutland@arm.com
Subject: Re: [PATCH v2] arm64: mm: Align PGDs to at least 64 bytes
Date: Tue, 29 Nov 2022 17:51:59 +0000 [thread overview]
Message-ID: <86edtlmyww.wl-maz@kernel.org> (raw)
In-Reply-To: <20221129143012.1806274-1-ardb@kernel.org>
On Tue, 29 Nov 2022 14:30:12 +0000,
Ard Biesheuvel <ardb@kernel.org> wrote:
>
> My copy of the ARM ARM (DDI 0487I.a) no longer describes the 64 byte
> minimum alignment of root page tables as being conditional on whether
> 52-bit physical addressing is supported and enabled, even though I seem
> to remember that this was the case formerly (and our code suggests the
> same).
>
> Section D17.2.144 "TTBR0_EL1, Translation Table Base Register 0 (EL1)"
> contains the following wording:
>
> ----Note----
> A translation table is required to be aligned to the size of the
> table. If a table contains fewer than eight entries, it must be
> aligned on a 64 byte address boundary
>
> So align pgd_t[] allocations to 64 bytes. Note that this change only
> affects 16k/4 levels configurations, which are unlikely to be in wide
> use.
>
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
After the VTTBR discussion, and to be extra sure of this, I reached
out to ARM and asked for clarification.
As it turns out, the omission of the "> 48 bits" restriction is an
unfortunate specification bug, and the old behaviour still applies
(Rule KBLCR is also wrong).
Can't wait for the next revision! ;-)
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2022-11-29 17:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-29 14:30 [PATCH v2] arm64: mm: Align PGDs to at least 64 bytes Ard Biesheuvel
2022-11-29 17:51 ` Marc Zyngier [this message]
2022-11-29 18:04 ` Ard Biesheuvel
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