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<86edttojcn.wl-maz@kernel.org> From: Marc Zyngier To: Icenowy Zheng Cc: Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Samuel Holland , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] irqchip/sifive-plic: drop quirk for two-cell variant In-Reply-To: <463d5effd271c002fb18fb3b8326321501c18782.camel@icenowy.me> References: <20221121042026.419383-1-uwu@icenowy.me> <86o7syoq4t.wl-maz@kernel.org> <16d01eebc1693916fc74e1e75458d6c0f080cf37.camel@icenowy.me> <86ilj5oltb.wl-maz@kernel.org> <402eb920c5ca84e7d751ec7bd9b7f4f512a66921.camel@icenowy.me> <86h6ypol03.wl-maz@kernel.org> <463d5effd271c002fb18fb3b8326321501c18782.camel@icenowy.me> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: uwu@icenowy.me, tglx@linutronix.de, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel@sholland.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221123_060711_081995_DB5E0FC7 X-CRM114-Status: GOOD ( 53.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gV2VkLCAyMyBOb3YgMjAyMiAxMzozNTo1OCArMDAwMCwKSWNlbm93eSBaaGVuZyA8dXd1QGlj ZW5vd3kubWU+IHdyb3RlOgo+IAo+IOWcqCAyMDIyLTExLTIz5pif5pyf5LiJ55qEIDEzOjMxICsw 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YzEwMCwgImFuZGVzdGVjaCxuY2VwbGljMTAwIiwgcGxpY19lZGdlX2luaXQpOwotSVJRQ0hJUF9E RUNMQVJFKHRoZWFkX2M5MDBfcGxpYywgInRoZWFkLGM5MDAtcGxpYyIsIHBsaWNfZWRnZV9pbml0 KTsKK0lSUUNISVBfREVDTEFSRShhbmRlc3RlY2hfbmNlcGxpYzEwMCwgImFuZGVzdGVjaCxuY2Vw bGljMTAwIiwgcGxpY19pbml0KTsKK0lSUUNISVBfREVDTEFSRSh0aGVhZF9jOTAwX3BsaWMsICJ0 aGVhZCxjOTAwLXBsaWMiLCBwbGljX2luaXQpOwoKLS0gCldpdGhvdXQgZGV2aWF0aW9uIGZyb20g dGhlIG5vcm0sIHByb2dyZXNzIGlzIG5vdCBwb3NzaWJsZS4KCl9fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LXJpc2N2IG1haWxpbmcgbGlzdApsaW51 eC1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21h aWxtYW4vbGlzdGluZm8vbGludXgtcmlzY3YK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26E69C433FE for ; Wed, 23 Nov 2022 14:09:38 +0000 (UTC) Received: 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t=1669212427; bh=HlVzEn9iVpO1hFWWoa7vvFL1MYhSqvFeHFhYnVxbf14=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OW4TEf8ZMiSTtnAuGUJQLLTa1FzN1XPIJUricYxhF114mqgOADjogR2hy73tQ5uLh d9wl52ojGwqyD77NyyC3Upw7XYm0rLFisN2DY6LIKJcrSU8bgzCbqF0E1+6pgxMzBQ /EVSOQXAGgygl1MG8p6jq7dFiZLJrqWaSm2mGAcKkgiOL0UYrjZJGDWQY+0wlsaEjw ciOXrMv4R6kTKm6NQZ9lv6GhGZlw3BpGrJHDnyfi6ZOSvECB0Hp5FS52ccifCvNz3z NHjHYwQoRJHmYYp2UNY0cKZCH87Gbg8IBfBtqDZaH/5FBNRcx/AyptSIuYQrTfjL4q QUsESlA+X9IMg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oxqP3-0088sj-7f; Wed, 23 Nov 2022 14:07:05 +0000 Date: Wed, 23 Nov 2022 14:07:04 +0000 Message-ID: <86edttojcn.wl-maz@kernel.org> From: Marc Zyngier To: Icenowy Zheng Cc: Thomas Gleixner , Palmer Dabbelt , Paul Walmsley , Samuel Holland , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] irqchip/sifive-plic: drop quirk for two-cell variant In-Reply-To: <463d5effd271c002fb18fb3b8326321501c18782.camel@icenowy.me> References: <20221121042026.419383-1-uwu@icenowy.me> <86o7syoq4t.wl-maz@kernel.org> <16d01eebc1693916fc74e1e75458d6c0f080cf37.camel@icenowy.me> <86ilj5oltb.wl-maz@kernel.org> <402eb920c5ca84e7d751ec7bd9b7f4f512a66921.camel@icenowy.me> <86h6ypol03.wl-maz@kernel.org> <463d5effd271c002fb18fb3b8326321501c18782.camel@icenowy.me> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: uwu@icenowy.me, tglx@linutronix.de, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel@sholland.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 23 Nov 2022 13:35:58 +0000, Icenowy Zheng wrote: >=20 > =E5=9C=A8 2022-11-23=E6=98=9F=E6=9C=9F=E4=B8=89=E7=9A=84 13:31 +0000=EF= =BC=8CMarc Zyngier=E5=86=99=E9=81=93=EF=BC=9A > > On Wed, 23 Nov 2022 13:16:01 +0000, > > Icenowy Zheng wrote: > > >=20 > > > =E5=9C=A8 2022-11-23=E6=98=9F=E6=9C=9F=E4=B8=89=E7=9A=84 13:13 +0000= =EF=BC=8CMarc Zyngier=E5=86=99=E9=81=93=EF=BC=9A > > > > On Wed, 23 Nov 2022 12:38:56 +0000, > > > > Icenowy Zheng wrote: > > > > >=20 > > > > > =E5=9C=A8 2022-11-22=E6=98=9F=E6=9C=9F=E4=BA=8C=E7=9A=84 17:28 +0= 000=EF=BC=8CMarc Zyngier=E5=86=99=E9=81=93=EF=BC=9A > > > > > > On Mon, 21 Nov 2022 04:20:26 +0000, > > > > > > Icenowy Zheng wrote: > > > > > > >=20 > > > > > > > As the special handling of edge-triggered interrupts are > > > > > > > defined in > > > > > > > the > > > > > > > PLIC spec, we can assume it's not a quirk, but a feature of > > > > > > > the > > > > > > > PLIC > > > > > > > spec; thus making it a quirk and use quirk-based codepath > > > > > > > is > > > > > > > not so > > > > > > > necessary. > > > > > >=20 > > > > > > It *is* necessary. > > > > > >=20 > > > > > > >=20 > > > > > > > Move to a #interrupt-cells-based practice which will allow > > > > > > > both > > > > > > > device > > > > > > > trees without interrupt flags and with interrupt flags work > > > > > > > for > > > > > > > all > > > > > > > compatible strings. > > > > > >=20 > > > > > > No. You're tying together two unrelated concepts: > > > > > >=20 > > > > > > - Edges get dropped in some implementations (and only some). > > > > > > You > > > > > > can > > > > > > =C2=A0 argue that the architecture allows it, but I see it is an > > > > > > =C2=A0 implementation bug. > > > > >=20 > > > > > As the specification allows it, it's not an implementation bug > > > > > -- > > > > > and > > > > > for those which do not show this problem, it's possible that > > > > > it's > > > > > just > > > > > all using the same trigger type (e.g. Rocket). > > > >=20 > > > > What are you against? The fact that this is flagged as a quirk? > > > > Honestly, I don't care about that. If we can fold all > > > > implementations > > > > into the same scheme, that's fine by me. > > >=20 > > > Then what should I do? > >=20 > > Make all edge-triggered interrupts use the edge flow. > >=20 > > >=20 > > > >=20 > > > > >=20 > > > > > >=20 > > > > > > - The need for expressing additional information in the > > > > > > interrupt > > > > > > =C2=A0 specifier is not necessarily related to the above. Other > > > > > > interrupt > > > > > > =C2=A0 controllers use extra cells to encode the interrupt > > > > > > affinity, > > > > > > for > > > > > > =C2=A0 example. > > > > >=20 > > > > > I think in these situations, if the interrupt controller does > > > > > not > > > > > contain any special handling for edge interrupts, we can just > > > > > describe > > > > > them as level ones in SW. > > > >=20 > > > > No, that's utterly wrong. We don't describe an edge as level. > > > > Ever. > > > >=20 > > > > >=20 > > > > > >=20 > > > > > > I want these two things to be kept separate. Otherwise, once > > > > > > we > > > > > > get > > > > > > some fancy ACPI support for RISCV (no, please...), we'll have > > > > > > to > > > > > > redo > > > > > > the whole thing... > > > > > >=20 > > > > > > > In addition, this addresses a stable version DT binding > > > > > > > violation - > > > > > > > - > > > > > > > Linux v5.19 comes with "thead,c900-plic" with #interrupt- > > > > > > > cells > > > > > > > defined to > > > > > > > be 1 instead of 2, this commit will allow DTs that complies > > > > > > > to > > > > > > > Linux > > > > > > > v5.19 binding work (although no such DT is devliered to the > > > > > > > public > > > > > > > now). > > > > > >=20 > > > > > > *That* is what should get fixed. > > > > >=20 > > > > > Supporting all stable versions' DT binding is our promise, I > > > > > think. > > > >=20 > > > > Absolutely. And I'm asking you to fix it. And only that. > > >=20 > > > Then what should I do? Mask this as another quirk that is only > > > applicable to c900-plic? > >=20 > > No. Make interrupts with a single cell use the level flow. >=20 > This sounds exactly like what we do in this patch now. No. Really not. If anything, you add more pointless crap. > Or, should we keep the quirk, and require both a flag cell containing > IRQ_TYPE_EDGE_RISING and an interrupt controller that matches the quirk > to use the special codepath for edge interrupts? This is becoming tedious. M. diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 2f4784860df5..6774ae19ad0b 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -60,13 +60,10 @@ #define PLIC_DISABLE_THRESHOLD 0x7 #define PLIC_ENABLE_THRESHOLD 0 =20 -#define PLIC_QUIRK_EDGE_INTERRUPT 0 - struct plic_priv { struct cpumask lmask; struct irq_domain *irqdomain; void __iomem *regs; - unsigned long plic_quirks; }; =20 struct plic_handler { @@ -208,9 +205,6 @@ static int plic_irq_set_type(struct irq_data *d, unsign= ed int type) { struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); =20 - if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) - return IRQ_SET_MASK_OK_NOCOPY; - switch (type) { case IRQ_TYPE_EDGE_RISING: irq_set_chip_handler_name_locked(d, &plic_edge_chip, @@ -244,9 +238,7 @@ static int plic_irq_domain_translate(struct irq_domain = *d, unsigned long *hwirq, unsigned int *type) { - struct plic_priv *priv =3D d->host_data; - - if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) + if (irq_fwspec->param_count >=3D 2) return irq_domain_translate_twocell(d, fwspec, hwirq, type); =20 return irq_domain_translate_onecell(d, fwspec, hwirq, type); @@ -335,9 +327,8 @@ static int plic_starting_cpu(unsigned int cpu) return 0; } =20 -static int __init __plic_init(struct device_node *node, - struct device_node *parent, - unsigned long plic_quirks) +static int __init plic_init(struct device_node *node, + struct device_node *parent) { int error =3D 0, nr_contexts, nr_handlers =3D 0, i; u32 nr_irqs; @@ -348,8 +339,6 @@ static int __init __plic_init(struct device_node *node, if (!priv) return -ENOMEM; =20 - priv->plic_quirks =3D plic_quirks; - priv->regs =3D of_iomap(node, 0); if (WARN_ON(!priv->regs)) { error =3D -EIO; @@ -471,20 +460,7 @@ static int __init __plic_init(struct device_node *node, return error; } =20 -static int __init plic_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, 0); -} - IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy syst= ems */ - -static int __init plic_edge_init(struct device_node *node, - struct device_node *parent) -{ - return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); -} - -IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_in= it); -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); +IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_init); +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); --=20 Without deviation from the norm, progress is not possible.