From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0101E215F42 for ; Tue, 4 Nov 2025 15:26:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762269973; cv=none; b=PPJNdQ1t8OX8/V3uS/Cwrgcs17dkThAMM2BRfY8Hz2lYvjg0zwe48vpPPpFNf95egOmvHEAIepU4nBK/FA0Ax+DupocMzzzyAa5lea6J+YHtNamrHxGO1kjx3xs/vQJchOdeej7mIXvl22yWRdRoKZOtJOuEUdWoIki5+RVaYVU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762269973; c=relaxed/simple; bh=ufkzVDQGpPkSO8Os+Cl/eseLg3hDFTXk0IeH26ebQdo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=f+Pe8qLWUp/IQpGjZq4gxGhPgE4glKU+AEMgB1sUccrHdhHDJhA51CjcK8d8ttFqiNOOjhgH2V1dh6quVbzu1Mv0G/7gQmVIIrVwHCZaUVOciXXo7JCmZ4ef53JiQJMOgvKx16dRAVMUxZdGS9rCHqyfxHWdJbWXSdpfdHIv/W8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H52LslPc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H52LslPc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5F0DAC4CEF7; Tue, 4 Nov 2025 15:26:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762269972; bh=ufkzVDQGpPkSO8Os+Cl/eseLg3hDFTXk0IeH26ebQdo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=H52LslPcO2hTqEixOFdfNeDNtilT+VxG966alxulMa9XNn1XeU7un4PJK37i/PvNE fmiN7iv29QOmbAnoVLZJwEl0ch4X5Jx1TKWHpvNcN+uil/FqqgR5e/Mi6YsjwQStKW ubIzumPimcM4dXYiOM8HYoCcpUZaeekdnI7l3WaacrvR9e2muOM8m3M1mSFjomJcnj C7+8KsM38fHGnYl+kTE5OsqgsnWwfgnqdtFhGcsd+u2s7nKulw/Kq898zMTPzBzFIp FON2/Q5dTW32nmtmZutiOyw9QqjtUwI1sLSFl3pDZXupEoT3icHrgfC+lE0tpFkkGX NNjBIY8DXQt4g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vGIvC-00000002KvX-1BnK; Tue, 04 Nov 2025 15:26:10 +0000 Date: Tue, 04 Nov 2025 15:26:09 +0000 Message-ID: <86fratvmy6.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com Subject: Re: [PATCH v1 3/8] KVM: arm64: Enable LS64 instructions when supported by guest In-Reply-To: <20251104125906.1919426-4-tabba@google.com> References: <20251104125906.1919426-1-tabba@google.com> <20251104125906.1919426-4-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 04 Nov 2025 12:59:01 +0000, Fuad Tabba wrote: > > The FEAT_LS64* family (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA) > enables support for LD64B, ST64B, and their variants. If a guest is > advertised these features, KVM should not trap accesses to these > instructions to EL2. > > This is controlled by the HCRX_EL2_EnASR, HCRX_EL2_EnALS, and > HCRX_EL2_EnAS0 bits. When clear, these bits trap the corresponding > instructions. KVM did not set them, which would cause guest-supported > instructions to trap. > > This also created a state mismatch for nested virtualization, which > validates its own HCRX_EL2 value against the features advertised in the > guest's ID_AA64ISAR1_EL1 (in handle_other()). > > Fix this by checking for each FEAT_LS64* variant in > vcpu_set_hcrx() and setting the corresponding HCRX_EL2 enable > bit if the guest supports the feature. > > Signed-off-by: Fuad Tabba Please see 20240815125959.2097734-1-maz@kernel.org, which has a large portion of what is required for this to work. Just flipping the bits isn't quite enough. Thanks, M. -- Without deviation from the norm, progress is not possible.