From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 977E21A2632 for ; Sat, 21 Jun 2025 09:51:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750499493; cv=none; b=rncrZsme7+fUmlF9ZHUqX/9ncjB1r5lj3rZo/LJZwWWaNs6kumNGobvK5UIHjh65kZEkDT0uUdHG+mJUq0tEja35MPrfhBorSDuz4RVbREFgNWeB02Hm6yrwicOWFMcdGSoKWuXfoipvkMuR//qnF1YLJQL7mPUrFZVZzpOsDdY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750499493; c=relaxed/simple; bh=zqxF9bnVwNKc/ifnO7BUR1j2CD2s9bRdDFAtKwWlYXo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=cfCSchNlySpn2T3ZUBE9oY+t+DTcxScD3tAYq+QmqiX3KgwORn5dDWhpDJ/sapATnxYAndtHQ5cmDq0nkqDspXadhEDt1rDh8inA3N/bozAY4B4xuEqQsQ1NHGmeiTNU7LgXvHbwj6XA3gLhkzzdWqb10hLAjLLgeIMEPPk6NyE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P6KY1QmJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P6KY1QmJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1634BC4CEE7; Sat, 21 Jun 2025 09:51:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750499493; bh=zqxF9bnVwNKc/ifnO7BUR1j2CD2s9bRdDFAtKwWlYXo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=P6KY1QmJmAJnnDk/EeANAKp+FuCt4SqzDY+tyVjD9tUdrTzx13gStKcmn63fTBcKO dgag4KUAK51OjTMM5ixP/cR0FPPZpGwfeLBk3ok4nwUVRyAaZ8m3VKup5H1DyrkCc9 8ma5EAnmCGWIU7G30bEvsIvWiVjoUIQ+bNrbe3Rwci0RfrJ75w3flbaE+4+W6Azw/G JjXAbM2ekoCVXNOHtQJvmyBFPhHXNmRaI/TQW4u+wUv6fpoymcuQ0HKrnemnkWYmZ2 nORsuOXwGcbJXIFs1FXJxabf415fcpi633/7RHgomc9IFT1yvS5CzjjqIhUDOkTPl0 WEEoz7jew+m/g== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uSusk-008mqn-OJ; Sat, 21 Jun 2025 10:51:30 +0100 Date: Sat, 21 Jun 2025 10:51:30 +0100 Message-ID: <86frftcti5.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu Subject: Re: [PATCH v2 05/27] KVM: arm64: nv: Respect exception routing rules for SEAs In-Reply-To: <20250616230308.1192565-6-oliver.upton@linux.dev> References: <20250616230308.1192565-1-oliver.upton@linux.dev> <20250616230308.1192565-6-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 17 Jun 2025 00:02:46 +0100, Oliver Upton wrote: > > Synchronous external aborts are taken to EL2 if ELIsInHost() or > HCR_EL2.TEA=1. Rework the SEA injection plumbing to respect the imposed > routing of the guest hypervisor and opportunistically rephrase things to > make their function a bit more obvious. > > Signed-off-by: Oliver Upton > --- > arch/arm64/include/asm/kvm_emulate.h | 14 +++++++-- > arch/arm64/kvm/emulate-nested.c | 9 ++++++ > arch/arm64/kvm/guest.c | 8 +++-- > arch/arm64/kvm/inject_fault.c | 45 +++++++++++----------------- > arch/arm64/kvm/mmio.c | 6 ++-- > arch/arm64/kvm/mmu.c | 15 +++------- > 6 files changed, 50 insertions(+), 47 deletions(-) > > diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h > index 19ffe9b0d3c1..1a0d51c74b42 100644 > --- a/arch/arm64/include/asm/kvm_emulate.h > +++ b/arch/arm64/include/asm/kvm_emulate.h > @@ -46,15 +46,25 @@ void kvm_skip_instr32(struct kvm_vcpu *vcpu); > > void kvm_inject_undefined(struct kvm_vcpu *vcpu); > void kvm_inject_vabt(struct kvm_vcpu *vcpu); > -void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr); > -void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr); > +int kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); > void kvm_inject_size_fault(struct kvm_vcpu *vcpu); > > +static inline int kvm_inject_sea_dabt(struct kvm_vcpu *vcpu, u64 addr) > +{ > + return kvm_inject_sea(vcpu, false, addr); > +} > + > +static inline int kvm_inject_sea_iabt(struct kvm_vcpu *vcpu, u64 addr) > +{ > + return kvm_inject_sea(vcpu, true, addr); > +} > + > void kvm_vcpu_wfi(struct kvm_vcpu *vcpu); > > void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu); > int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2); > int kvm_inject_nested_irq(struct kvm_vcpu *vcpu); > +int kvm_inject_nested_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); > > static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu) > { > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 1de4a9001d9d..aa5527ddf506 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -2811,3 +2811,12 @@ int kvm_inject_nested_irq(struct kvm_vcpu *vcpu) > /* esr_el2 value doesn't matter for exits due to irqs. */ > return kvm_inject_nested(vcpu, 0, except_type_irq); > } > + > +int kvm_inject_nested_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) > +{ > + u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, > + iabt ? ESR_ELx_EC_IABT_LOW : ESR_ELx_EC_DABT_LOW); > + esr |= ESR_ELx_FSC_EXTABT | ESR_ELx_IL; > + > + return kvm_inject_s2_fault(vcpu, esr); I think this may be slightly abusive. R_FKLWR gives a list of all faults that populate HPFAR_EL2, and SEA isn't one of them. I think only populating ESR/FAR should be enough, and avoid leaking stale fault addresses from arch.fault.hpfar_el2. > +} > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index 2196979a24a3..dd5cce0006f3 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -839,6 +839,7 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, > bool serror_pending = events->exception.serror_pending; > bool has_esr = events->exception.serror_has_esr; > bool ext_dabt_pending = events->exception.ext_dabt_pending; > + int ret; Initialise ret to 0... > > if (serror_pending && has_esr) { > if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) > @@ -852,8 +853,11 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, > kvm_inject_vabt(vcpu); > } > > - if (ext_dabt_pending) > - kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu)); > + if (ext_dabt_pending) { > + ret = kvm_inject_sea_dabt(vcpu, kvm_vcpu_get_hfar(vcpu)); > + if (ret < 0) > + return ret; ... drop this test ... > + } > > return 0; ... and return ret? Otherwise, LGTM. M. -- Without deviation from the norm, progress is not possible.