From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 499E7C31E46 for ; Wed, 12 Jun 2019 07:35:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2070220874 for ; Wed, 12 Jun 2019 07:35:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="qU5uQvcf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2070220874 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qYqUVpmYCTFJBLq/beuDhNEtyvDNVD/huo39CBFknNQ=; b=qU5uQvcf0U5IPk 5pQfaGokgA1SAXnkGVaU9IALTxPdLbh+GM2BZQUNFSgB68L9wM5twjOmKhI+3aJGBrvcz0Uq2nl0G wyagIImXMFlPn2ZGEjKIyWMu4eoD1b0+Bi1m6ZFQdTZgG2PTfkVl6H7SEASb6XUmbIKFFSPnxNlxY R8lCkmmxxCwwWFzs/THLf7tvincNeJu93spowxxqBW9rrocMO//JYM+8pGEUYMRmKzNES9u3ijXhi DakmytnCU6glwwIXoOwvOqGdy5cNSZFs+IxpR7H53WEO7VG3Yd3qm1okUp98H4PXP1iCKPcX/nXR5 ZmQNDHpZ7kFrCpY9ui2A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1haxnU-000585-Kw; Wed, 12 Jun 2019 07:35:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1haxnR-00057U-Kc for linux-arm-kernel@lists.infradead.org; Wed, 12 Jun 2019 07:35:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 741552B; Wed, 12 Jun 2019 00:35:47 -0700 (PDT) Received: from big-swifty.misterjones.org (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B636F3F246; Wed, 12 Jun 2019 00:35:42 -0700 (PDT) Date: Wed, 12 Jun 2019 08:35:41 +0100 Message-ID: <86ftofgss2.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Thomas Gleixner Subject: Re: [RFC 0/2] Add workaround for core wake-up on IPI for i.MX8MQ In-Reply-To: References: <20190610121346.15779-1-abel.vesa@nxp.com> <20190610131921.GB14647@lakrids.cambridge.arm.com> <20190610132910.srd4j2gtidjeppdx@fsr-ub1664-175> <6f1052ea-623a-b2e8-9aa8-22aef5fab4ca@arm.com> <20190610135514.xd5myavjsloos2y3@fsr-ub1664-175> <7b86aa90-6d64-589c-f11e-d2ee6ab3fd54@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190612_003549_722845_9D675354 X-CRM114-Status: GOOD ( 15.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "devicetree@vger.kernel.org" , Lorenzo Pieralisi , Abel Vesa , Carlo Caione , Fabio Estevam , Sascha Hauer , "linux-kernel@vger.kernel.org" , Rob Herring , Jacky Bai , dl-linux-imx , Pengutronix Kernel Team , Abel Vesa , Leonard Crestez , Shawn Guo , "linux-arm-kernel@lists.infradead.org" , Lucas Stach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 12 Jun 2019 08:14:16 +0100, Thomas Gleixner wrote: > On Mon, 10 Jun 2019, Leonard Crestez wrote: > > On 6/10/2019 5:08 PM, Marc Zyngier wrote: > > > Nobody is talking about performance here. It is strictly about > > > correctness, and what I read about this system is that it cannot > > > reliably use cpuidle. > > My argument was that it's fine if PPIs and LPIs are broken as long as > > they're not used: > > > > * PPIs are only used for local timer which is not used for wakeup. > > Huch? The timer has to bring the CPU out of idle as any other > interrupt. They use a separate hack for that, pretending that the timer is stopped during idle (it isn't), and setup a broadcast timer when entering idle. That timer uses an interrupt that can wake-up the target CPU, and all is well in the world. Sort of. Of course, this breaks as PPIs are not only used by the timer, but also by a number of other HW bits (PMU, GIC, guest and hypervisor timers), and they don't have corresponding hacks to back them up. Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [RFC 0/2] Add workaround for core wake-up on IPI for i.MX8MQ Date: Wed, 12 Jun 2019 08:35:41 +0100 Message-ID: <86ftofgss2.wl-marc.zyngier@arm.com> References: <20190610121346.15779-1-abel.vesa@nxp.com> <20190610131921.GB14647@lakrids.cambridge.arm.com> <20190610132910.srd4j2gtidjeppdx@fsr-ub1664-175> <6f1052ea-623a-b2e8-9aa8-22aef5fab4ca@arm.com> <20190610135514.xd5myavjsloos2y3@fsr-ub1664-175> <7b86aa90-6d64-589c-f11e-d2ee6ab3fd54@arm.com> Mime-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Thomas Gleixner Cc: Mark Rutland , "devicetree@vger.kernel.org" , Lorenzo Pieralisi , Abel Vesa , Carlo Caione , Fabio Estevam , Sascha Hauer , "linux-kernel@vger.kernel.org" , Rob Herring , Jacky Bai , dl-linux-imx , Pengutronix Kernel Team , Abel Vesa , Leonard Crestez , Shawn Guo , "linux-arm-kernel@lists.infradead.org" , Lucas Stach List-Id: devicetree@vger.kernel.org On Wed, 12 Jun 2019 08:14:16 +0100, Thomas Gleixner wrote: > On Mon, 10 Jun 2019, Leonard Crestez wrote: > > On 6/10/2019 5:08 PM, Marc Zyngier wrote: > > > Nobody is talking about performance here. It is strictly about > > > correctness, and what I read about this system is that it cannot > > > reliably use cpuidle. > > My argument was that it's fine if PPIs and LPIs are broken as long as > > they're not used: > > > > * PPIs are only used for local timer which is not used for wakeup. > > Huch? The timer has to bring the CPU out of idle as any other > interrupt. They use a separate hack for that, pretending that the timer is stopped during idle (it isn't), and setup a broadcast timer when entering idle. That timer uses an interrupt that can wake-up the target CPU, and all is well in the world. Sort of. Of course, this breaks as PPIs are not only used by the timer, but also by a number of other HW bits (PMU, GIC, guest and hypervisor timers), and they don't have corresponding hacks to back them up. Thanks, M. -- Jazz is not dead, it just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8D0CC31E46 for ; Wed, 12 Jun 2019 07:35:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A0528206BA for ; Wed, 12 Jun 2019 07:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731382AbfFLHfy (ORCPT ); Wed, 12 Jun 2019 03:35:54 -0400 Received: from foss.arm.com ([217.140.110.172]:46516 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726778AbfFLHfx (ORCPT ); Wed, 12 Jun 2019 03:35:53 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 741552B; Wed, 12 Jun 2019 00:35:47 -0700 (PDT) Received: from big-swifty.misterjones.org (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B636F3F246; Wed, 12 Jun 2019 00:35:42 -0700 (PDT) Date: Wed, 12 Jun 2019 08:35:41 +0100 Message-ID: <86ftofgss2.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Thomas Gleixner Cc: Leonard Crestez , Abel Vesa , Lucas Stach , Mark Rutland , Abel Vesa , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jacky Bai , Lorenzo Pieralisi , dl-linux-imx , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Carlo Caione Subject: Re: [RFC 0/2] Add workaround for core wake-up on IPI for i.MX8MQ In-Reply-To: References: <20190610121346.15779-1-abel.vesa@nxp.com> <20190610131921.GB14647@lakrids.cambridge.arm.com> <20190610132910.srd4j2gtidjeppdx@fsr-ub1664-175> <6f1052ea-623a-b2e8-9aa8-22aef5fab4ca@arm.com> <20190610135514.xd5myavjsloos2y3@fsr-ub1664-175> <7b86aa90-6d64-589c-f11e-d2ee6ab3fd54@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 12 Jun 2019 08:14:16 +0100, Thomas Gleixner wrote: > On Mon, 10 Jun 2019, Leonard Crestez wrote: > > On 6/10/2019 5:08 PM, Marc Zyngier wrote: > > > Nobody is talking about performance here. It is strictly about > > > correctness, and what I read about this system is that it cannot > > > reliably use cpuidle. > > My argument was that it's fine if PPIs and LPIs are broken as long as > > they're not used: > > > > * PPIs are only used for local timer which is not used for wakeup. > > Huch? The timer has to bring the CPU out of idle as any other > interrupt. They use a separate hack for that, pretending that the timer is stopped during idle (it isn't), and setup a broadcast timer when entering idle. That timer uses an interrupt that can wake-up the target CPU, and all is well in the world. Sort of. Of course, this breaks as PPIs are not only used by the timer, but also by a number of other HW bits (PMU, GIC, guest and hypervisor timers), and they don't have corresponding hacks to back them up. Thanks, M. -- Jazz is not dead, it just smells funny.