From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53B2E44683D; Tue, 14 Jul 2026 16:39:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784047166; cv=none; b=AjH8wBGL5s7yrrACrrlAyD3F6+nKk28Qad5gwTL3yaziHuC7zJZG1euxHbtcrhHXThDNuFei/8Z00fczMRTx1iWs1cOqzcgsf2ec7nxPIXPM68i8exdFWkBBel2TJ0LbZn+GQ30eDyQSmqiQ0yv9loNgD9KXznlEtQYVKjH2A90= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784047166; c=relaxed/simple; bh=bsxJpR5wDiivHUv3aLXncU0530cj1WK5KPaC9EOTATo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=TFcFYj23FHen4+lXRIl5WNPcYXHApXrJuvSUyjHS394rYI9B262zI4Ka+ZnwMyrEdl0p5EVVYf3qzhlIsWMsiS2ESpL9GnjdQiMmIbHVib9LrNTmCjZE7mR0Hfql5ugAP6IFBfQn78GZGIcsm9IQvi83rBdKpc/wMERn1ZIMJPU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nUgf5F08; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nUgf5F08" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04CB21F000E9; Tue, 14 Jul 2026 16:39:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784047165; bh=Hn8NTRPyBX62oV5on+JtdYo+ZRCD1JmGN69q5ZlqxJc=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=nUgf5F08NcozlkcfQ61bxhdKjMCscOI1Bt4Xj9NMYv+edk1Iba8FfJNU4oKz2K+4p F8xKvnizHMWIccbQ2WsIFf+1VqI5g3EssRjAZuMwnd4lyDLPlDcu7R+Rb/5dKBRMQm /nzzUMecrvoYT75KUGYBcSdF3FykiRKlxRBwN8bidLEwD4LdCofU0PEmuKJokYCR8H aTNTHU53rLz09cC6zflx26k9+fYblieig2FlFzkKN+cQJVr1jWoDvhI7rT84alRVlX E7Se4EI1AvJ4qo/HFae1d3XBpFzku81uh8MJu4NNwueyZQ6zEvwqQcJxJaVDRVEAow ME4Av5Wbkzd+w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wjgAE-00000004zBP-45mZ; Tue, 14 Jul 2026 16:39:23 +0000 Date: Tue, 14 Jul 2026 17:39:22 +0100 Message-ID: <86h5m1o79h.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: Oliver Upton , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas , Will Deacon , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Vincent Donnefort , Quentin Perret , Sebastian Ene , Hyunwoo Kim Subject: Re: [PATCH v5 2/8] KVM: arm64: Make vcpu_{read,write}_sys_reg available to HYP code In-Reply-To: References: <20260714101601.4142645-1-fuad.tabba@linux.dev> <20260714101601.4142645-3-fuad.tabba@linux.dev> <86ik6hoayl.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: fuad.tabba@linux.dev, oupton@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, joey.gouly@arm.com, seiden@linux.ibm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, vdonnefort@google.com, qperret@google.com, sebastianene@google.com, imv4bel@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 14 Jul 2026 16:32:54 +0100, Fuad Tabba wrote: > > On Tue, 14 Jul 2026 at 16:19, Marc Zyngier wrote: > > > > On Tue, 14 Jul 2026 11:15:55 +0100, > > Fuad Tabba wrote: > > > > > > The vcpu_{read,write}_sys_reg() accessors are only valid on a VHE host, > > > so helpers built on them such as kvm_vcpu_set_be()/kvm_vcpu_is_be() > > > cannot be shared with hyp code. exception.c already wraps them in local > > > helpers that pick the host- or hyp-side accessor via has_vhe(). > > > > > > Rename the host-only implementations to __vcpu_{read,write}_sysreg_vhe() > > > > I'm a bit puzzled by this. There is nothing that makes these functions > > VHE-specific. Look at where they are called from: plenty of non-VHE > > uses. These helpers are the canonical accessors for any system > > register, and they don't cater for any particular mode. > > I might have misunderstood what Oliver asked me to do here [1]: > > Can you instead name the wrappers vcpu_{read,write}_sys_reg() and rename > > the current implementations, like __vcpu_{read,write}_sysreg_vhe()? > > Since they're only used and gated by has_vhe(), they're vhe-specific? But they factually aren't VHE specific. Look at sys_reg.c, for example. The whole point is that they abstract where the registers are located, irrespective of the KVM mode. The code in exception.c is actually a local specialisation of this code for the nVHE code not to explode. And the exact same effect could be achieved without repainting the whole thing and renaming *perfectly named* accessors! ;-) Something like below (compile-tested only). M. diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h index 9d9e7674d45fe..5ea708ff29436 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -526,6 +526,14 @@ static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu) return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK; } +#if defined (__KVM_NVHE_HYPERVISOR__) +#define vcpu_read_sys_reg(v, r) __vcpu_sys_reg(v, r) +#define vcpu_write_sys_reg(v, x, r) __vcpu_assign_sys_reg(v, x, r) +#elif defined (__KVM_VHE_HYPERVISOR__) +#define vcpu_read_sys_reg(v, r) vcpu_read_sys_reg(v, r) +#define vcpu_write_sys_reg(v, x, r) vcpu_write_sys_reg(v, x, r) +#endif + static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu) { if (vcpu_mode_is_32bit(vcpu)) { diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index bef40ddb16dbc..754e2dc1df54a 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -20,22 +20,6 @@ #error Hypervisor code only! #endif -static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) -{ - if (has_vhe()) - return vcpu_read_sys_reg(vcpu, reg); - - return __vcpu_sys_reg(vcpu, reg); -} - -static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) -{ - if (has_vhe()) - vcpu_write_sys_reg(vcpu, val, reg); - else - __vcpu_assign_sys_reg(vcpu, reg, val); -} - static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode, u64 val) { @@ -101,14 +85,14 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, switch (target_mode) { case PSR_MODE_EL1h: - vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL1); - sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1); - __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1); + vbar = vcpu_read_sys_reg(vcpu, VBAR_EL1); + sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); + vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL1); break; case PSR_MODE_EL2h: - vbar = __vcpu_read_sys_reg(vcpu, VBAR_EL2); - sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL2); - __vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2); + vbar = vcpu_read_sys_reg(vcpu, VBAR_EL2); + sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL2); + vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2); break; default: /* Don't do that */ @@ -185,7 +169,7 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, */ static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode) { - u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1); + u32 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); unsigned long old, new; old = *vcpu_cpsr(vcpu); @@ -281,7 +265,7 @@ static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) { unsigned long spsr = *vcpu_cpsr(vcpu); bool is_thumb = (spsr & PSR_AA32_T_BIT); - u32 sctlr = __vcpu_read_sys_reg(vcpu, SCTLR_EL1); + u32 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1); u32 return_address; *vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode); @@ -305,7 +289,7 @@ static void enter_exception32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset) if (sctlr & (1 << 13)) vect_offset += 0xffff0000; else /* always have security exceptions */ - vect_offset += __vcpu_read_sys_reg(vcpu, VBAR_EL1); + vect_offset += vcpu_read_sys_reg(vcpu, VBAR_EL1); *vcpu_pc(vcpu) = vect_offset; } -- Without deviation from the norm, progress is not possible.