From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9563713B293 for ; Tue, 4 Nov 2025 15:15:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762269354; cv=none; b=DfD+Ordzqd72hXtSvqUmTYlzctsoYWmGurIl3KLwDrHaI97k92l3w8TejljZfNG2NA2ULHea2ZvB+wQKnamTXzVb5B3xzqPRpR3q2gsS0Rdbg/3uk14z0vJCPK7oRN9AmbnGUsHCESrFWpI5Jr1a8r9Ysvi/kCObrimgVioTZHY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762269354; c=relaxed/simple; bh=z4gLYdJzEW4GjlUvstMoQfV2hJ358bwR0e9XXreUMe4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Qttrm2yHfnA+vuMY7JhcpgwbNnPBX55MCIBkizvRpDPPO2Gt2qO2sDNf+KLzDnAiDVrkUf2Aj0db063siU3T9rVG2YnLTU402MpMXo47cs4UgJ/bjiIZ++iEQCZA4QlxH4cduv1G+KoKn/PwCSIxBhPHmn77n8Xt5rEgSw8dk3s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cKjai/u3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cKjai/u3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1BC1BC116B1; Tue, 4 Nov 2025 15:15:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762269354; bh=z4gLYdJzEW4GjlUvstMoQfV2hJ358bwR0e9XXreUMe4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=cKjai/u3WEmrF0qoL4fCe1Nngh5Pl1Zg0wiQ/QT3YTLDo7X1BDgt35Qk/a+lQ56yD KdHUFLOcQ5XfiCjQbvbZq2nDWGj3ihi2Wuy9Z/0QqTxed700UwZMrC97/1X0+1ltzf Jk5qOzId4J/PSH83A/xNrIZb8R9UjVyq/ojtmvTX2mW02jQk3AJfiRr1JV/lYGu2UK CTmW5kZwt+6ar2i8A9baqopAW7zsFrAKbl6iGKAfMFMTI/Te3fGnGAmCmOsjx4/zkg SWnmj8eMagfm0cvmJlkgTHkCd8P9iKVvjGIvOZatIuOdwO2YbBxgFcaI/XKDHIR0ef OHZ0dcgZWn2uw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vGIlD-00000002Kft-2rtZ; Tue, 04 Nov 2025 15:15:51 +0000 Date: Tue, 04 Nov 2025 15:15:51 +0000 Message-ID: <86h5v9vnfc.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com Subject: Re: [PATCH v1 2/8] KVM: arm64: Trap access to ALLINT if FEAT_NMI not supported by the guest In-Reply-To: <20251104125906.1919426-3-tabba@google.com> References: <20251104125906.1919426-1-tabba@google.com> <20251104125906.1919426-3-tabba@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, will@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, vladimir.murzin@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 04 Nov 2025 12:59:00 +0000, Fuad Tabba wrote: > > Access to ALLINT is part of FEAT_NMI. If a guest does not support this > feature, any access to this register must be trapped to the hypervisor > (EL2). > > KVM didn't configure this trap, potentially allowing a guest to toggle > all interrupt mask when it doesn't support FEAT_NMI. Fix this by > checking if the guest has FEAT_NMI support. > > Signed-off-by: Fuad Tabba > --- > arch/arm64/include/asm/kvm_emulate.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h > index 0f8311263edf..3fc62808c548 100644 > --- a/arch/arm64/include/asm/kvm_emulate.h > +++ b/arch/arm64/include/asm/kvm_emulate.h > @@ -688,6 +688,9 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) > else > vcpu->arch.hcrx_el2 |= HCRX_EL2_MCE2; > > + if (!kvm_has_feat(kvm, ID_AA64PFR1_EL1, NMI, IMP)) > + vcpu->arch.hcrx_el2 |= HCRX_EL2_TALLINT; > + > if (kvm_has_tcr2(kvm)) > vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; > I think this is moving in the wrong direction. We have for quite some time now tried to automatically derive these behaviours from the guest config, as we do for FGUs. I would like to see a similar behaviour being introduced for non-FGT bits so that we don't have to worry about these things anymore. Thanks, M. -- Without deviation from the norm, progress is not possible.