From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91B471917F1 for ; Wed, 18 Dec 2024 16:57:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734541024; cv=none; b=sTC5PNuNKQgCXqXqto8lTcLwWEsGf/RvwtRmIqEXFInosw0QTzWFrWkH6gfa0y0GraHto6VWfwd29H8ltCUAizFXXDbfZ92/af0Ge48hJlT+rxAJHE3pPCu+61r5av2u0pAdxdxl7gyQ6nqQiNk20+o3QLa+mvLb3Kz7X0/5N0s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734541024; c=relaxed/simple; bh=W5I+c8BU2jlkCC/viGtloqXYWpj/NJYSnADUyBcOXTg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=KALOKclYeVL9kr4Zr81um+YPCwQ9N/CDR1JZ+Hux5SsSwznmwdzZ62eSOPGwACmDRZgDfI4N7evpazvPjl1rfx/7VGldpz219xp1+cFf0BVsI1cu4qf+XMwIfKFumatDBtljHcGvymGWvn/hWziiGag/rqte+k2kjie0WGmSwPk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EqBhIS53; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EqBhIS53" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2231DC4CECD; Wed, 18 Dec 2024 16:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734541024; bh=W5I+c8BU2jlkCC/viGtloqXYWpj/NJYSnADUyBcOXTg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=EqBhIS53aMg1xCKU3ADtLwe52eblQTEiq/DPcm9dss1bYjP4Dp8sUSeHc2MbafCbu VjaR19INxto3cgxMupkKab6YvkpMJWwMuO1YmjERIx6SKeRO5fawhDQzMuUMNosk4G pT2CxmzAOmXh/jKENxxYh1rwQ05cwB4FQYU7kFNu3gpHjumEOJbRtlJufug1sVQfT9 NqD6xLlr3FmVMlDC2S8rFeWmdB1P1k6d5g2SH5se9sHTIfVgYPvkprVwj74xh30bNk q96trjT+7jetL3bxboHrZcqACO3+5LAh8eT4e9sPZCLbzRYnrQ6d8QeuOe8fwwsqb+ L4eIQJhqQansg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tNxM5-0050X1-Tc; Wed, 18 Dec 2024 16:57:02 +0000 Date: Wed, 18 Dec 2024 16:57:01 +0000 Message-ID: <86h671q68y.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , James Clark Subject: Re: [PATCH 0/4] KVM: arm64: PMU fixes for 6.13 In-Reply-To: <20241217175336.3657966-1-oliver.upton@linux.dev> References: <20241217175336.3657966-1-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mizhang@google.com, coltonlewis@google.com, rananta@google.com, james.clark@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 17 Dec 2024 17:53:32 +0000, Oliver Upton wrote: > > Small set of fixes for PMU, mostly focused on plugging gaps in nested > support that I'd missed last time around: > > - Don't attempt to enable/disable EL2 counters when PMCR_EL0.E is > changed. This is already the case since the enable state of a > counter is re-evaluated in kvm_pmu_create_perf_event(), though the > handling of PMCR_EL0.E would suggest otherwise. > > - Enable/disable EL2 counters when MDCR_EL2.HPME is changed. > > - Only reset 'guest' counters when PMCR_EL0.P is set, excluding EL2 > counters from being reset. > > Applies to 6.13-rc3, tested on the M2 w/ my PMUv3 patches thrown on top. > > Oliver Upton (4): > KVM: arm64: Add unified helper for reprogramming counters by mask > KVM: arm64: Use KVM_REQ_RELOAD_PMU to handle PMCR_EL0.E change > KVM: arm64: nv: Reload PMU events upon MDCR_EL2.HPME change > KVM: arm64: Only apply PMCR_EL0.P to the guest range of counters > > arch/arm64/kvm/pmu-emul.c | 89 +++++++++++++++------------------------ > arch/arm64/kvm/sys_regs.c | 32 +++++++++++--- > include/kvm/arm_pmu.h | 6 +-- > 3 files changed, 62 insertions(+), 65 deletions(-) Reviewed-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.