From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8854F12DD8F for ; Mon, 3 Jun 2024 13:48:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717422522; cv=none; b=Wuwz9mE17odPOehKVl5i4fr535UNbcOSslmpuRn4mLQCFKFfGqQZ6bL9m/Z2qJT1/rhi2O0L0kFQWKJ6D5WsgYiB/O9rG/kE+VkE8KFbysZWB6xbNsKICMAJkFy3jVK5kk4/+CQphMTnymFtLIeGllctYothlLoMMdo8Sgw5sfA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717422522; c=relaxed/simple; bh=OG8wlGk5A5Mk4O1zQ8c8YqPHyiunct/EJFpPZjb2H04=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=eQxotS5dLEC39T6eKLxSKOi8HkumMBaQGhMCyJiNAyeSXu9F1QrtpBa8xKH5T97GPqdcFD5xs0TOa4HDYSyqAaexjf5VJkaTCe6Nri737gRCaVo8hJ5zU1gnmY/nre652Xll5C4bM4iXWR709ZQyeZ75FCJ5356Cy8qs7Jo7aoA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=K6ejc8MQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="K6ejc8MQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18F24C32781; Mon, 3 Jun 2024 13:48:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717422522; bh=OG8wlGk5A5Mk4O1zQ8c8YqPHyiunct/EJFpPZjb2H04=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=K6ejc8MQsRX8xrhaj2kCcu4DmXlJhQcdEgc5SVtf9DAuRKZOoC/zcNBh/o8wSR/WC IRAG/g5ySDPkWUfpR4mZRm0XSex8a/MvNWtfc2JFIppjZjS571JGK4Di5Oz4mrhYPo o6BZob++XXOSqoXUq73kSFqWenHxE2MD7HOEP4UYluylCYvcoVoSLRebQ/0ArL1BCN BW/h5Oq+wSDVXqLaLlOJ/LdTaCfY0Z7eNqPu4wU1jFEWgG4jQU+MT8GXBG7UcY5gcO EsD+O/+nlVtojDVPa+Edu8OW1thfivhhy+wtsbNSosnsMffuuyl0oNC8Xyy+E5Z+YY E6wrD3v0IGuTQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sE83D-000FWL-OC; Mon, 03 Jun 2024 14:48:39 +0100 Date: Mon, 03 Jun 2024 14:48:39 +0100 Message-ID: <86jzj6kuh4.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Fuad Tabba , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, qperret@google.com, seanjc@google.com, alexandru.elisei@arm.com, catalin.marinas@arm.com, philmd@linaro.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, mark.rutland@arm.com, joey.gouly@arm.com, rananta@google.com, yuzenghui@huawei.com Subject: Re: [PATCH v3 05/11] KVM: arm64: Eagerly restore host fpsimd/sve state in pKVM In-Reply-To: <6e473418-dbce-4008-94fe-f60174d3f8fe@sirena.org.uk> References: <20240528125914.277057-1-tabba@google.com> <20240528125914.277057-6-tabba@google.com> <6e473418-dbce-4008-94fe-f60174d3f8fe@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, qperret@google.com, seanjc@google.com, alexandru.elisei@arm.com, catalin.marinas@arm.com, philmd@linaro.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, mark.rutland@arm.com, joey.gouly@arm.com, rananta@google.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 03 Jun 2024 14:27:07 +0100, Mark Brown wrote: >=20 > On Mon, Jun 03, 2024 at 09:37:16AM +0100, Fuad Tabba wrote: > > On Fri, May 31, 2024 at 3:09=E2=80=AFPM Mark Brown = wrote: > > > On Tue, May 28, 2024 at 01:59:08PM +0100, Fuad Tabba wrote: >=20 > > > > + write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2); >=20 > > > As well as the sync issue Oliver mentioned on the removal of > > > _cond_update() just doing these updates as a blind write creates a > > > surprise if we ever get more control bits in ZCR_EL2. >=20 > > I'm not sure it does. The other bits are RES0, and this is always > > setting the length. So even if new control bits are added, this > > shouldn't matter. >=20 > The surprise would be that if new control bits were added this would > result in clearing them on restore. And as far as I can tell, there is no in-flight architectural change that touches this class of registers. And should this eventually happens, we will have to audit *all* the spots when ZCR_ELx is touched and turn them all into RMW accesses. Having an extra spot here isn't going to change this in a material way. >=20 > > Also, one of the concerns in terms of performance is now with > > nested-virt support being added, and the overhead of doing the > > conditional update when we know that it's unlikely that anyone is > > implementing vectors as big as the max. >=20 > I guess there's the option of doing a restore of a value fixed during > initialisation instead? And what do we gain from that? >=20 > > > > + /* > > > > + * On saving/restoring host sve state, always use the maximum= VL for > > > > + * the host. The layout of the data when saving the sve state= depends > > > > + * on the VL, so use a consistent (i.e., the maximum) host VL. > > > > + * > > > > + * Setting ZCR_EL2 to ZCR_ELx_LEN_MASK sets the effective len= gth > > > > + * supported by the system (or limited at EL3). > > > > + */ > > > > + write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL2); >=20 > > > Setting ZCR_ELx_LEN_MASK sets the VL to the maximum supported/configu= red > > > for the current PE, not the system. This will hopefully be the same > > > since we really hope implementors continue to build symmetric systems > > > but there is handling for that case in the kernel just in case. Given > > > that we record the host's maximum VL should we use it? >=20 > > You're right, but even if the current PE had a different vector > > length, ZCR_ELx_LEN_MASK is the default value for ZCR_EL2 when the > > host is running (this is the existing behavior before this patch > > series). It is also the value this patch series uses when saving the > > host SVE state. So since we are consistent I think this is correct. >=20 > The reason we just set all bits in ZCR_EL2.LEN is that we don't > currently use SVE at EL2 so we're just passing everything through to EL1 > and letting it worry about things. As we start adding more SVE code at > EL2 we need to care more and I think we should start explicitly > programming what we think we're using to use to avoid surprises. For > example in this series we allocate the buffer used to store the host SVE > state based on the probed maximum usable VL for the system but here we > use whatever the PE has as the maximum VL. This means that in the > (hopefully unlikely) case where the probed value is lower than the PE > value we'll overflow the buffer. In that case, we need the *real* maximum across all CPUs, not the maximum usable. M. --=20 Without deviation from the norm, progress is not possible. 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