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From: Torbjorn Granlund <tg@gmplib.org>
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Date: Wed, 08 May 2013 11:20:48 +0200
In-Reply-To: <20130508065009.GP5000@ohm.aurel32.net> (Aurelien Jarno's message
	of "Wed\, 8 May 2013 08\:50\:09 +0200")
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Subject: Re: [Qemu-devel] [Qemu-ppc] Incorrect handling of more PPC64 insns
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To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson <rth@twiddle.net>

Aurelien Jarno <aurelien@aurel32.net> writes:

  64-bit CPUs check for the L bit of comparison instruction to determine
  if the instruction is 32-bit wide, and not to the MSR SF bit.
=20=20
  L=3D1 on a 32-bit CPU should generate an invalid instruction exception.
=20=20
No.  See my previous post.

The L bit is to be ignored for 32-bit CPUs, just like the original code
did.

--=20
Torbj=C3=B6rn