From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1418E2EEE60; Wed, 24 Jun 2026 09:57:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782295060; cv=none; b=ryTX1o3KOjlqNocciHSI/KV/zHbR+2Qp6GtF7Vcd+hD1jF1QxTyAUKO7o1vgvjPZi61yK4E38P+UHemxgJw0IyV4TftYEDd45UKvhzQc3mse+pMB0XkN0GdL7CzZirjljCds1mnHwcr5ZaU86HNAzDiV4iLiN5/Hsey+kYkELRM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782295060; c=relaxed/simple; bh=jd69DKk+cUdKUb+eN989Djf4zanqOEdHJ55xxecHLEQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=fkKLWBu6M8a8V8yCQF1IaZ4sEg7IslW2aKfhPoLNe5PigSVVgq1IruOsDTs7C3xUZr7nTkAMG7ZicK74tOu97tMXOfjYgSUZgPst+9KgkIh+yZN/AmYFLgZ2PrAzvRwXcXrcg5XfmZrpeF5uDKMKGeh4hzGXuUrL1hhkGTCmrls= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zjat725x; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zjat725x" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B99511F000E9; Wed, 24 Jun 2026 09:57:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1782295058; bh=xGOCGGfz/+i5zRbNpzkCtwa5vuOnFRMn+9rFacWY9MY=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=Zjat725x4cestm3WggsvO1tUcPrtk1vIcmSQNd49F6us/98RxVaouxlCg05qypzXw 74yBgfN43VsQpyAMZndLZuyNN4hgMv3+wro4c/MxOnRT3WeJFE+JfnGX11bCghFhas Gfb83oAx3+paL2jGGODz3h+VOIAFiLMJjyAIwmbhowezAC6/TESL7nR293KXAVScVx LDa6GJUtdZPeVtfjxc3qSCYjRIz8fDTcEm2dQXuDx4RncPy+9jhbMLGeHyvwj0ZCds GxnHy1s4LR53gqRvQ6Tr0fR5KEBIShV+lUJLpyyxD91m28pBQjcVpEfcUmAqmycPkq RluCqkqvb4iUQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wcKMS-0000000Fa86-26jv; Wed, 24 Jun 2026 09:57:36 +0000 Date: Wed, 24 Jun 2026 10:57:36 +0100 Message-ID: <86ldc4qmzz.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: sashiko-reviews@lists.linux.dev, kvmarm@lists.linux.dev Subject: Re: [PATCH] KVM: arm64: nv: Check RW permissions for insn abort due to S1PTW In-Reply-To: References: <20260623211310.1529760-1-oupton@kernel.org> <20260623213225.A89CF1F000E9@smtp.kernel.org> <86mrwkqqix.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@kernel.org, sashiko-reviews@lists.linux.dev, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 24 Jun 2026 10:39:43 +0100, Oliver Upton wrote: > > On Wed, Jun 24, 2026 at 09:41:26AM +0100, Marc Zyngier wrote: > > > diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h > > > index 5bf3d7e1d92c..d5c61e0027c8 100644 > > > --- a/arch/arm64/include/asm/kvm_emulate.h > > > +++ b/arch/arm64/include/asm/kvm_emulate.h > > > @@ -479,21 +479,12 @@ static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) > > > > > > static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu) > > > { > > > - if (kvm_vcpu_abt_iss1tw(vcpu)) { > > > - /* > > > - * Only a permission fault on a S1PTW should be > > > - * considered as a write. Otherwise, page tables baked > > > - * in a read-only memslot will result in an exception > > > - * being delivered in the guest. > > > - * > > > - * The drawback is that we end-up faulting twice if the > > > - * guest is using any of HW AF/DB: a translation fault > > > - * to map the page containing the PT (read only at > > > - * first), then a permission fault to allow the flags > > > - * to be set. > > > - */ > > > - return kvm_vcpu_trap_is_permission_fault(vcpu); > > > - } > > > + /* > > > + * The architecture sucks; assume that the S1PTW fetched for write if > > > + * HA is enabled at stage-1. > > > + */ > > > + if (kvm_vcpu_abt_iss1tw(vcpu)) > > > + return effective_tcr_ha(vcpu); > > > > OK, so you're trading the implicit state machine (translation fault -> > > RO, permission fault -> RW) for a direct TCR.HA lookup, because the > > only reason you'd get a S1PTW fault for write is if you were updating > > the descriptor. This is cute, and I wish I had thought of that, as it > > saves us a round trip. > > > > But why can't that happen with HD? Surely this results in a similar > > fault, and I think we should also evaluate that bit. > > The effective value of both HAFT and HD is 0 if TCR_ELx.HA is 0. So > evaluating HA covers them all :) Indeed it does! Maybe worth capturing in a comment, because it isn't completely obvious (we have R_SNVTX for HAFT, but you need to dive into the TCR_EL1 register description to read the blurb about the effective value of HD). Thanks, M. -- Without deviation from the norm, progress is not possible.