From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 210D41D435F for ; Fri, 10 Oct 2025 09:22:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760088142; cv=none; b=gKU3afmXfvHbvMPVNRAt0l7bbI4ocsX9XwzrDSsKY70MLWply86sntUkt+sxHi/vB9n3XT7ERhnvHZU/t2yA6rjyDixEGbqdcwNdYfb6erMsvQyP0wBQgMuu/e4qCEf5/t0WFPG2PqgzhbquNoxdBjE6cPjQ0hpTTOnvAU7st+Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760088142; c=relaxed/simple; bh=GnUz7C2zbtjR0soOdMoHNTAX8aSovVUPvkVFgOsxrd0=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=hiaQHYhcnIUkTbX/MxaqWgSLTqSZTISLzdq9S36Kil7NPWdcKZsE5YZixMowyXHPBPCdQT7+/TnH0gZwzz7A8vBr7P8alasvUdaQaUcHce9wq8WwazwAm5Rwi5J3cL+aLaSjHqgR8BYpwYF0bJ62UUkhZJWLPhvRTcQ/33HCFXY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RNllekUP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RNllekUP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C559C4CEF1; Fri, 10 Oct 2025 09:22:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760088141; bh=GnUz7C2zbtjR0soOdMoHNTAX8aSovVUPvkVFgOsxrd0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=RNllekUPLupnQUjBWe7O1Tv6b7WAgSgbKekXIW/ibqKFivdEtRnyJOf/bZNq/4HUo 6NklNZJhrU3+QHJH2wGuk1iM4DI3awD0G6Igr63O/+ZUZx++bGBsnIeVZr5h84kbsw py7AcTs8WQJx0t3im7mtVwUAaSLGx0VRduRC+ZVig0z/ZuXWsoUMvS/b76VYl+B52s ltc2FyAeAOPMYDqeChz2ya/K42qehFcJU6I63Fgh1p/OfHM8dlUOm1mo0AhtV56j2S dTEYT3YGMSJLSyShkT4T7/fu+958JwDnGDihlpwreJYZLABfVWFRTl5BKFgjsMj+yr kUd5wxqFZNaVw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v79KM-0000000CruH-3pns; Fri, 10 Oct 2025 09:22:19 +0000 Date: Fri, 10 Oct 2025 10:22:18 +0100 Message-ID: <86ldljxgad.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Will Deacon , Catalin Marinas , Mark Rutland , Jan Kotas Subject: Re: [PATCH] arm64: Revamp HCR_EL2.E2H RES1 detection In-Reply-To: References: <20251009121239.29370-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, jank@cadence.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 09 Oct 2025 22:30:34 +0100, Oliver Upton wrote: > > Hey, > > On Thu, Oct 09, 2025 at 01:12:39PM +0100, Marc Zyngier wrote: > > We currently have two ways to identify CPUs that only implement FEAT_VHE > > and not FEAT_E2H0: > > > > - either they advertise it via ID_AA64MMFR4_EL1.E2H0, > > - or the HCR_EL2.E2H bit is RAO/WI > > > > However, there is a third category of "cpus" that fall between these > > two cases: on CPUs that do not implement FEAT_FGT, it is IMPDEF whether > > an access to ID_AA64MMFR4_EL1 can trap to EL2 when the register value > > is zero. > > > > A consequence of this is that on systems such as Neoverse V2, a NV > > guest cannot reliably detect that it is in a VHE-only configuration > > (E2H is writable, and ID_AA64MMFR0_EL1 is 0), despite the hypervisor's > > best effort to repaint the id register. > > > > Replace the RAO/WI test by a sequence that makes use of the VHE > > register remnapping between EL1 and EL2 to detect this situation, > > and work out whether we get the VHE behaviour even after having > > set HCR_EL2.E2H to 0. > > > > This solves the NV problem, and provides a more reliable acid test > > for CPUs that do not completely follow the letter of the architecture > > while providing a RES1 behaviour for HCR_EL2.E2H. > > > > Suggested-by: Marc Rutland > ^~~~ > > Thank you *Mark* for the suggestion here, neat trick :) Too many Mar[ck]s. I'm struggling! ;-) > I'd be in favor of this patch being sent to stable, happy to handle the > backports if you don't have the time for it. VMs mysteriously dying > isn't a very good experience on NV and I'd like to not scare folks away. I think Mark (yes, him!) had a plan to backport some of the !FEAT_E2H0 patches back to earlier kernels. I'll let him comment on that. > Reviewed-by: Oliver Upton Thanks! M. -- Without deviation from the norm, progress is not possible.