From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2F381DE2B6 for ; Thu, 17 Oct 2024 13:38:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729172332; cv=none; b=jfRZJuFZAFP8z62boZwY0MNiNovBkM+i38qIlZuUz0Vfamx7foRGBJg1289M5dmfMzlbOU+jP9O4m9d5HcEM/B6kBN8JnnUQJ4n1wgztBRzR/nic0wd8rq2+8h2L7NSV2Zn55NQuin+qOBD7vyYh8j8s89xRNftegFKZFsNpH18= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729172332; c=relaxed/simple; bh=RdyZ0ZrCOYPugG2NlUcTxnZuhG9u9UEX/RSwZ8q4PXc=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=lm5uTwrKDCz9zTCxXfzhhgkRZ3WYQBSSD7jidvM7DqkFPwHXgt7EvgPKsc8OmNmim4T5ncxSLX1O5UCvgNsLEn9O9+uAsqwZZmjgyHmg8JYXKqD3u4uGZF1X7L7CVFZsACdJM6flUarb1YazWlXs9JKYmT8xqxcSKqRfT9qZ4ek= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YYHOZvOw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YYHOZvOw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AAA20C4CEC3; Thu, 17 Oct 2024 13:38:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729172331; bh=RdyZ0ZrCOYPugG2NlUcTxnZuhG9u9UEX/RSwZ8q4PXc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=YYHOZvOwM8MaDqYU9QCbiPCI07tU9xTHq4vVOpd+Cm54ShcFC6KFLqlG7b4Yfa5bX ggqelNp3FqGf5XWE3zUt3mlxvX/X8kbOtUCm/ipw00EPZ7BhW1hqzuYzDBGnH9c1eT DAWGJ17mmz6qPxqfi16Ey0+UrvJCpJJie9REp69IYpFJV00LbR95fT7EhTYzOBhDl2 EfEKbPuztwoDwmDaEBblsG+EEYzdZaLwXr3y0sIuhOF8oRqmSHIrVk3CdQfEAK3z1z ISn4oALQnZBAgKTZHt74n+JsssQ5D76FcJE3+fG5lRfHa46hmMtIHGF57f9MvF335C QqDSj+krggWTA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1t1QiH-004Ssv-Ev; Thu, 17 Oct 2024 14:38:49 +0100 Date: Thu, 17 Oct 2024 14:38:49 +0100 Message-ID: <86ldym4zo6.wl-maz@kernel.org> From: Marc Zyngier To: Joey Gouly Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, anshuman.khandual@arm.com, james.morse@arm.com, Oliver Upton , Suzuki K Poulose , Zenghui Yu , Jing Zhang , Shameerali Kolothum Thodi , Catalin Marinas , Will Deacon Subject: Re: [PATCH v5 4/7] KVM: arm64: Fix missing traps of guest accesses to the MPAM registers In-Reply-To: <20241017130638.GA139029@e124191.cambridge.arm.com> References: <20241015133923.3910916-1-joey.gouly@arm.com> <20241015133923.3910916-5-joey.gouly@arm.com> <86msj33py6.wl-maz@kernel.org> <20241017130638.GA139029@e124191.cambridge.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: joey.gouly@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, anshuman.khandual@arm.com, james.morse@arm.com, oliver.upton@linux.dev, suzuki.poulose@arm.com, yuzenghui@huawei.com, jingzhangos@google.com, shameerali.kolothum.thodi@huawei.com, catalin.marinas@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 17 Oct 2024 14:06:38 +0100, Joey Gouly wrote: > > Hi Marc, > > Thanks for looking! > > On Thu, Oct 17, 2024 at 12:54:09PM +0100, Marc Zyngier wrote: > > On Tue, 15 Oct 2024 14:39:20 +0100, > > Joey Gouly wrote: > > > > > > @@ -204,6 +205,35 @@ static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu) > > > __deactivate_fgt(hctxt, vcpu, kvm, HAFGRTR_EL2); > > > } > > > > > > +static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu) > > > +{ > > > + u64 r = MPAM2_EL2_TRAPMPAM0EL1 | MPAM2_EL2_TRAPMPAM1EL1; > > > + > > > + if (!cpus_support_mpam()) > > > + return; > > > + > > > + /* trap guest access to MPAMIDR_EL1 */ > > > + if (mpam_cpus_have_mpam_hcr()) { > > > + write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2); > > > + } else { > > > + /* From v1.1 TIDR can trap MPAMIDR, set it unconditionally */ > > > + r |= MPAM2_EL2_TIDR; > > > + } > > > + > > > + write_sysreg_s(r, SYS_MPAM2_EL2); > > > > Please use the write_sysreg_el2() accessor, so that VHE under NV has > > an easier time, should we ever get there. > > Are you suggesting this, to avoid a trap (and instead get the register-memory > redirection)? > > The two reasons I could see to keep it as-is: > - The name changes from MPAM2_EL2 to MPAM1_EL1 (1 and 2 suffixes after > MPAM) Arghhh. > - It's setting trap behaviour, which is an EL2 concept (and are RES0 > bits in the MPAM1_EL1 reg). Other trap registers such as HCRX_EL2 use > that register directly, however they don't have an _EL1 counterpart so have to. Arghhh again. So this is yet another register that doesn't match FEAT_NV2p1, by having RES0 fields in its EL2-equivalent-EL1 register, and we can't even use MPAM1_EL1 for NV. > I'm fine to change it, just want to clarify before I do. Nah, don't bother. This thing can't be rescued. Thanks for the gory details! M. -- Without deviation from the norm, progress is not possible.