From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3FE386346; Mon, 24 Feb 2025 08:32:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740385941; cv=none; b=OPtymn9whMeI+yFrc7cClaRpxQBc9UUFcTn8VfC7jwJXyFAIuPvARa/6mIIGfkPlk52uMIwwZc6f9jxCw18zBXVbAUG2sIBKwhVLwd2nRn6Z0kTKtRa1iELWCKAi/+B7NcoGk1zqS+4LxEGVaaj/P5tHeCWojC4gQEfg4gTMi3s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740385941; c=relaxed/simple; bh=bSIM8Tbz1K1m9Pb52yVWvSYNTf02AU2E2IBRGGRNYbQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=XS78BzlxP93aHSf8kCAN2xUumDXfxjL45kjYwDrQ+cqUvNQQ+lVgEjZrrrJ6RrZTdyONn7+9F/S0t65PTm17bzse+wsg48ejthEX+QdkBIFqFNdIoLH2ovJ1fbltq3Bdh3ymp108axHGoO6GzSOOd2B+2d8xJYV6AXJQ3E8XGuc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BcSNtHCn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BcSNtHCn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 319F5C4CED6; Mon, 24 Feb 2025 08:32:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740385941; bh=bSIM8Tbz1K1m9Pb52yVWvSYNTf02AU2E2IBRGGRNYbQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=BcSNtHCnhtceHL5Bwzxat3ETiQjWBIJmf2OLiXb20jM+redompi1shfQ10Xhnn58U 6aLAQn8OA52F/MRt2kOANae3vI+aHsVckMTLLFHQSgpd19rmdzdYvuumhlrDrIQBCJ 7023J9BwcrzgS/e4qCH7TwNUpGNbj6bCPJBuLzfB/w5EOSxjgoBYxYpKA3f8ttpEPh a9rVogdkW7A9udrRDqJsjigC2mX+uR6GGYgrBRqNYZzuxr9t9mK/DcPWS7fWe11oQl EfCovrN/LHeCoh7a4ADLfslzo/Opwvxe+r1Y2juwGPVNxZN/risKsrR5TbHPlgdfnU 0DIvHbgQr+cVw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tmTsx-007EJK-6t; Mon, 24 Feb 2025 08:32:19 +0000 Date: Mon, 24 Feb 2025 08:32:18 +0000 Message-ID: <86msebrbe5.wl-maz@kernel.org> From: Marc Zyngier To: Aneesh Kumar K.V Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Eric Auger Subject: Re: [PATCH 03/14] KVM: arm64: Mark HCR.EL2.E2H RES0 when ID_AA64MMFR1_EL1.VH is zero In-Reply-To: References: <20250215173816.3767330-1-maz@kernel.org> <20250215173816.3767330-4-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: aneesh.kumar@kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 24 Feb 2025 07:39:30 +0000, Aneesh Kumar K.V wrote: > > Marc Zyngier writes: > > > Enforce HCR_EL2.E2H being RES0 when VHE is disabled, so that we can > > actually rely on that bit never being flipped behind our back. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/nested.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c > > index 0c9387d2f5070..ed3add7d32f66 100644 > > --- a/arch/arm64/kvm/nested.c > > +++ b/arch/arm64/kvm/nested.c > > @@ -1034,6 +1034,8 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu) > > res0 |= (HCR_TEA | HCR_TERR); > > if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) > > res0 |= HCR_TLOR; > > + if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP)) > > + res0 |= HCR_E2H; > > if (!kvm_has_feat(kvm, ID_AA64MMFR4_EL1, E2H0, IMP)) > > res1 |= HCR_E2H; > > > > Does it make sense to check for E2H0 if MMFR1_EL1.VH == 0 ? > Should the above check be > if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP)) > res0 |= HCR_E2H; > else if (!kvm_has_feat(kvm, ID_AA64MMFR4_EL1, E2H0, IMP)) > res1 |= HCR_E2H; What difference does it make? This bit can only have a reserved value, and can never be actively modified. If you *really* wanted to optimise this for reasons that I really cannot fathom, you could have this: if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP)) res0 |= HCR_E2H; else res1 |= HCR_E2H; because that's what we really implement. Does it matter? I don't think so. If anything, I'd rather we keep the code as is and have a run-time warning if a bit is simultaneously RES0 and RES1, because that'd be indicative of a much bigger problem. Thanks, M. -- Without deviation from the norm, progress is not possible.