From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7ED833F7 for ; Sun, 21 Apr 2024 10:30:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713695412; cv=none; b=Ex4HupbxN7YLclX8o9c8jtHJQOeiNOK2MmlClR8D86++T1dQJrYLNtcTordAnrLNl9nXNptalue+eBsDV2ISSJnr8AiaVejnNPQe56H/Fgs/h1VAFal3V124ZKXaIJ+bBGK9C3ZzrFB3eHvpXT2UtZAoe0V0PdvydYcCd91yWKg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713695412; c=relaxed/simple; bh=1XOqPZETFyNpmyua7ut3L/5x+o4LUqf4zkl3dtaG4ag=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Oe94wo2rYF2bcWGP+FsZnFLL9lfzDBfSeuH3jy3hq+lz+wFf0+XVW0MP5iixi7IsZCLXwxvnlGT8slW8uSvWtj6iWPzAnKD1GtrcJi7b4NGI6xoZg5DEjgD5oTCWBGkPOt2Pij6EV9aNS8MEX2n+Pc00WG1oz0rSZvZraiFFVoI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gq59IsJs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gq59IsJs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B4F2C113CE; Sun, 21 Apr 2024 10:30:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713695412; bh=1XOqPZETFyNpmyua7ut3L/5x+o4LUqf4zkl3dtaG4ag=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Gq59IsJsnD8sFCU0VwqvRFIflsdcaa/0evXCHe5wJac2RA4dJavixVtTjhsKAZ8ar C6I/NppRyvlwMoSkkJ/153qjHXeKAuFKUWKJSlSlcZDsb3nTnMhAK3DDgimbook7xo b4QoOaromWjYjVavSCYzVGsnNLRgB5TiXrAIxj3DlE8zuz+ibC1413UnnuexlGXIDG 4kdwswcXxSicV6cuOM3cnXE5sfkAZXKdRvbYTJ1Py/B4m8Qsoi6EA+mtJ1LD47096J pi67PV/LpkZJ1mtrOw8CJpiLxYClMKwBfSPznHnx+lTgQrRniGBuo3K5wytdEXIigN ABTu5MYeSrKKw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1ryUSY-006WS2-1V; Sun, 21 Apr 2024 11:30:10 +0100 Date: Sun, 21 Apr 2024 11:30:09 +0100 Message-ID: <86mspnqa8e.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, James Morse , Suzuki K Poulose , Zenghui Yu , Eric Auger Subject: Re: [PATCH v2 09/19] KVM: arm64: vgic-its: Maintain a translation cache per ITS In-Reply-To: <20240419223842.951452-10-oliver.upton@linux.dev> References: <20240419223842.951452-1-oliver.upton@linux.dev> <20240419223842.951452-10-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 19 Apr 2024 23:38:32 +0100, Oliver Upton wrote: > > Within the context of a single ITS, it is possible to use an xarray to > cache the device ID & event ID translation to a particular irq > descriptor. Take advantage of this to build a translation cache capable > of fitting all valid translations for a given ITS. > > Signed-off-by: Oliver Upton > --- > arch/arm64/kvm/vgic/vgic-its.c | 26 +++++++++++++++++++++++++- > include/kvm/arm_vgic.h | 6 ++++++ > 2 files changed, 31 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c > index be17a53d16ef..fd576377c084 100644 > --- a/arch/arm64/kvm/vgic/vgic-its.c > +++ b/arch/arm64/kvm/vgic/vgic-its.c > @@ -530,6 +530,11 @@ static struct vgic_its *__vgic_doorbell_to_its(struct kvm *kvm, gpa_t db) > return iodev->its; > } > > +static unsigned long vgic_its_cache_key(u32 devid, u32 eventid) > +{ > + return (((unsigned long)devid) << 32) | eventid; > +} > + > static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist, > phys_addr_t db, > u32 devid, u32 eventid) > @@ -583,6 +588,7 @@ static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its, > u32 devid, u32 eventid, > struct vgic_irq *irq) > { > + unsigned long cache_key = vgic_its_cache_key(devid, eventid); > struct vgic_dist *dist = &kvm->arch.vgic; > struct vgic_translation_cache_entry *cte; > unsigned long flags; > @@ -592,6 +598,9 @@ static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its, > if (irq->hw) > return; > > + if (xa_reserve_irq(&its->translation_cache, cache_key, GFP_KERNEL_ACCOUNT)) > + return; > + This thing tickles me a bit. What does it mean from the PoV of the caller? That although we have missed in the cache initially, someone else is populating it? The final code reads like this: if (xa_reserve_irq(&its->translation_cache, cache_key, GFP_KERNEL_ACCOUNT)) return; xa_lock_irqsave(&its->translation_cache, flags); rcu_read_lock(); /* * We could have raced with another CPU caching the same * translation behind our back, so let's check it is not in * already */ db = its->vgic_its_base + GITS_TRANSLATER; if (__vgic_its_check_cache(kvm, db, devid, eventid)) goto out; Does it mean we could drop this check? And even relax the locking? Thanks, M. -- Without deviation from the norm, progress is not possible.