From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE071946B for ; Wed, 8 Feb 2023 11:20:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C1E4C433D2; Wed, 8 Feb 2023 11:20:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1675855219; bh=B6zrD3MUb4KtKj9xfIe7UkOC0UIDN9V3CX8L2Her3GU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=aWxLzIYYde9IiprCgOyv9OMXKegfvQyUEOixFqlEkX2XfCCFIGDz4bmWGktTPsikQ E5/kt7GfLGfuqb9ld8GSk74tHMWQ2se+9SVmO9xsiW9XUtJa/k/D8UGcvA3Xo8t4So lh+aiOr7TChS/1mdrm3zVIGf6eX/TyC0HNRG629pi+Y13pVPbVuo5w6Bhm2g72pAZL msu+rL/AXB1bDzTFdMUliSA0quO2kp+rxCp4Q0EJtZJA+X0qNS9X05rZzfKBMpzaW4 mkWPEKQGNS9CcvvT3l5ACVcJVR3mIqrodWR33V+FEAfhGKhydboVL4rCAoODRawMBw NqHT970latq/w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pPiUr-008dkz-Ci; Wed, 08 Feb 2023 11:20:17 +0000 Date: Wed, 08 Feb 2023 11:20:16 +0000 Message-ID: <86mt5oz9n3.wl-maz@kernel.org> From: Marc Zyngier To: Zaid Al-Bassam Cc: Jesus Sanchez-Palencia , Russell King , Catalin Marinas , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu Subject: Re: [PATCH 3/8] perf: pmuv3: Add common defines for the PMU version In-Reply-To: <20230126204444.2204061-4-zalbassam@google.com> References: <20230126204444.2204061-1-zalbassam@google.com> <20230126204444.2204061-4-zalbassam@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zalbassam@google.com, jesussanp@google.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 26 Jan 2023 20:44:39 +0000, Zaid Al-Bassam wrote: > > The current PMU version defines are available for arm64 only, > As we want to add PMUv3 support to arm (32-bit), this patch makes > these defines available for both arm/arm64 by defining them in > the common arm_pmuv3.h header. > > Signed-off-by: Zaid Al-Bassam > --- > drivers/perf/arm_pmuv3.c | 8 ++++---- > include/linux/perf/arm_pmuv3.h | 6 ++++++ > 2 files changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index 94e4098b662d..505f0758260c 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -392,7 +392,7 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { > */ > static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) > { > - return (cpu_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5); > + return (cpu_pmu->pmuver >= ARMV8_PMU_DFR_VER_V3P5); This doesn't really makes any sense. As per the architecture spec, PMUv3p5 on AArch32 cannot expose the top 32 bits (DDI0487I.a, G8.4.10 "PMEVCNTR, Performance Monitors Event Count Registers, n = 0 - 30"): There is no means to access bits [63:32] directly from AArch32 state. So on AArch32, this should always return false, no ifs, no buts. Also, turning the architectural symbols (ID_AA64DFR0_EL1_*) into custom stuff is a total non-starter. We generate these names and want to use them everywhere. Either you abstract them in the architecture specific headers, or you define the AArch64 name in the AArch32 code. Thanks, M. -- Without deviation from the norm, progress is not possible. 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Wed, 08 Feb 2023 11:20:17 +0000 Date: Wed, 08 Feb 2023 11:20:16 +0000 Message-ID: <86mt5oz9n3.wl-maz@kernel.org> From: Marc Zyngier To: Zaid Al-Bassam Cc: Jesus Sanchez-Palencia , Russell King , Catalin Marinas , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu Subject: Re: [PATCH 3/8] perf: pmuv3: Add common defines for the PMU version In-Reply-To: <20230126204444.2204061-4-zalbassam@google.com> References: <20230126204444.2204061-1-zalbassam@google.com> <20230126204444.2204061-4-zalbassam@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zalbassam@google.com, jesussanp@google.com, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230208_032022_931154_7D968C0A X-CRM114-Status: GOOD ( 24.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 26 Jan 2023 20:44:39 +0000, Zaid Al-Bassam wrote: > > The current PMU version defines are available for arm64 only, > As we want to add PMUv3 support to arm (32-bit), this patch makes > these defines available for both arm/arm64 by defining them in > the common arm_pmuv3.h header. > > Signed-off-by: Zaid Al-Bassam > --- > drivers/perf/arm_pmuv3.c | 8 ++++---- > include/linux/perf/arm_pmuv3.h | 6 ++++++ > 2 files changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index 94e4098b662d..505f0758260c 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -392,7 +392,7 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { > */ > static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) > { > - return (cpu_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5); > + return (cpu_pmu->pmuver >= ARMV8_PMU_DFR_VER_V3P5); This doesn't really makes any sense. As per the architecture spec, PMUv3p5 on AArch32 cannot expose the top 32 bits (DDI0487I.a, G8.4.10 "PMEVCNTR, Performance Monitors Event Count Registers, n = 0 - 30"): There is no means to access bits [63:32] directly from AArch32 state. So on AArch32, this should always return false, no ifs, no buts. Also, turning the architectural symbols (ID_AA64DFR0_EL1_*) into custom stuff is a total non-starter. We generate these names and want to use them everywhere. Either you abstract them in the architecture specific headers, or you define the AArch64 name in the AArch32 code. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel