From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5C59262D32; Tue, 11 Mar 2025 19:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741720218; cv=none; b=WbT2ux0SzH3SlQekhft8mFvN0K43GpHLNOKNiwMC6S/FS8ekfMDWFCCW8xRN0tdUBvPSab9nf7rROJ+VugLpDLtqrpRsplIfpAjlSS+CxMhdfOPho4KBkDsYeWOPiHdNgpAOveOUi340qexeYjkGTT4ZuBeC7ncO0z6Q5htfMAo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741720218; c=relaxed/simple; bh=99llKZilnJT4E48a+3LamgB6gGoSVPp37FNJyrkf0Kg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=OCVbtQdfGU4uaQu8x8pWm5f6+EX/Cz0Vi73GBsh70KF5C2BBZeEe9TP0/Ga016Xy0nj9Thot+svx5jTEcbzlPXullfDDHwvFMiCHGKWPHmz6PHaFzLf7c4nH9OnZdhoBXIqpGZL8VZciNkOY5LfX/0VMamUsaGD+Cb9ZZBLxAes= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PLJbEYRG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PLJbEYRG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4BC3AC4CEE9; Tue, 11 Mar 2025 19:10:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741720216; bh=99llKZilnJT4E48a+3LamgB6gGoSVPp37FNJyrkf0Kg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PLJbEYRG4EeWGAuA9hC0NNMyistSYTBPThKkYGpYGldf7MG+l9BssZSuQInQXLkCN FzkJ2UMDsqloXvKn5QYwff0zQ3/A4VZL+zHUZNLX9zQTBZ1hH3LNdJYtUi//v0tgjc lqOKwDEC7NE4u8Xfsr+lq2zSy+5NfjtcRd4JsLGwkblxFSV+cRenG+6Osocidgo5O8 l5kOHGrzSDFyPbt3tXVNA+4jW9+i3pDCwT2yQWOHdwE4UWFVbub+JDbtw1WJM1q2SR S649RQbvOJeGbTxuRpbvz4AB5ypaXX1QoCvMeri6WCX1axQnOpdpXi+vDWIK+g4gnm g0SD1MzaFXNdw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1ts4zW-00Cf5J-BY; Tue, 11 Mar 2025 19:10:14 +0000 Date: Tue, 11 Mar 2025 19:10:14 +0000 Message-ID: <86o6y7o02x.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland Subject: Re: [PATCH 07/18] KVM: arm64: Compute FGT masks from KVM's own FGT tables In-Reply-To: References: <20250210184150.2145093-1-maz@kernel.org> <20250210184150.2145093-8-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 04 Mar 2025 16:55:50 +0000, Fuad Tabba wrote: > > Hi Marc, > > On Mon, 10 Feb 2025 at 18:42, Marc Zyngier wrote: > > > > In the process of decoupling KVM's view of the FGT bits from the > > wider architectural state, use KVM's own FGT tables to build > > a synthitic view of what is actually known. > > synthitic -> synthetic Ah, I missed that one earlier. Will fix. > > > > This allows for some checking along the way. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_arm.h | 4 ++ > > arch/arm64/include/asm/kvm_host.h | 14 ++++ > > arch/arm64/kvm/emulate-nested.c | 102 ++++++++++++++++++++++++++++++ > > 3 files changed, 120 insertions(+) > > > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > > index 8d94a6c0ed5c4..e424085f2aaca 100644 > > --- a/arch/arm64/include/asm/kvm_arm.h > > +++ b/arch/arm64/include/asm/kvm_arm.h > > @@ -359,6 +359,10 @@ > > #define __HAFGRTR_EL2_MASK (GENMASK(49, 17) | GENMASK(4, 0)) > > #define __HAFGRTR_EL2_nMASK ~(__HAFGRTR_EL2_RES0 | __HAFGRTR_EL2_MASK) > > > > +/* Because the sysreg file mixes R and W... */ > > +#define HFGRTR_EL2_RES0 HFGxTR_EL2_RES0 (0) > > +#define HFGWTR_EL2_RES0 (HFGRTR_EL2_RES0 | __HFGRTR_ONLY_MASK) > > __HFGRTR_ONLY_MASK is a hand-crafted bitmask. The only bit remaining > in HFGxTR_EL2 that is RES0 is bit 51. If that were to be used as an > HFGRTR-only bit without __HFGRTR_ONLY_MASK getting updated, then > aggregate_fgt() below would set its bit in hfgwtr_masks. Could this be > a problem if this happens and the polarity of this bit ends up being > negative, thereby setting the corresponding nmask bit? So I ended up doing exactly what I threatened to do, which is to completely get rid of the HFGxTR nonsense, and bring HFG{R,W}TR to their full glory. The diffstat is a bit annoying: arch/arm64/include/asm/el2_setup.h | 14 +-- arch/arm64/include/asm/kvm_arm.h | 4 +- arch/arm64/include/asm/kvm_host.h | 3 +- arch/arm64/kvm/emulate-nested.c | 154 ++++++++++++------------- arch/arm64/kvm/hyp/include/hyp/switch.h | 4 +- arch/arm64/kvm/hyp/vgic-v3-sr.c | 8 +- arch/arm64/kvm/nested.c | 42 +++---- arch/arm64/kvm/sys_regs.c | 20 ++-- arch/arm64/tools/sysreg | 194 ++++++++++++++++++++------------ 9 files changed, 250 insertions(+), 193 deletions(-) but at least it puts all registers in the same bucket, and we don't assume anything anymore. I'll repost the series on Monday, once I'm on holiday. Thanks, M. -- Without deviation from the norm, progress is not possible.