From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A74E3D53E for ; Sun, 21 Apr 2024 09:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713693263; cv=none; b=lC1PQP5fevbBITt4KCZ7FL+yO+h9W+dMNEgkMP544gKPOzC8QSUi4VeCmitDXcrhPNMd+PrCCwxfzupIR6ygxELjI44isXP6JTCpsNhdKitjOwPFk3sCWpdtEMoaC250h8eEt8KcpX2aZfkL5J/EyNXQHVEsh1/N2FcSje11V9Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713693263; c=relaxed/simple; bh=yKZDKqhbwFu4n13B571jpPwl1i1u8xh5AVNphrBX/Jw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=K9Fix1Ww9vhRr/sYCmPAH61yG2oVtWyuAseVtluwieqCf9ge3d26Ts5iVy9xdvNLJNK3k/Ji7/eNxifO0DF+78+VanL2+GFBFy7RHQQQF3jCAiUON7V04fcgnwO4pea7SZUsnbRbe9Y/o2o2mFIDot3TLGgMPdNeWavPKesQgik= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tEKSK1p9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tEKSK1p9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47EFBC113CE; Sun, 21 Apr 2024 09:54:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1713693263; bh=yKZDKqhbwFu4n13B571jpPwl1i1u8xh5AVNphrBX/Jw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=tEKSK1p9QAKIYuSSUSUCNkkCCD5w7iVo/qwjRf+rYZ161lBXKU40f05ZElwxMd9YO fdLtOBy0z0UsCJM6CKFXLQYawAeflj/Z/fiLmiigRoF+cz2R8LLfqse40NrCTMy+r/ KeUyPGXJxUTW725Ur3bEdOOka+Ukm/6k+RUEOOMHsu/yPDsphLUiumyZTmJOLwzMSW H6AUxAwZvT1CQ6Kp9RiuTvO1edP39VLrKHxO7Vb2KXDYFDsgKp0hv4n2VXsk9rrrC1 yEvRFpbYLrd4nfLhOl2E1g94y6HOF5E3xyD/aez+FL6pTVVdh3CZSZI/irWO2Mp4Rt Q6paI6q3WpFqg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1ryTts-006VyR-RJ; Sun, 21 Apr 2024 10:54:21 +0100 Date: Sun, 21 Apr 2024 10:54:20 +0100 Message-ID: <86o7a3qbw3.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, James Morse , Suzuki K Poulose , Zenghui Yu , Eric Auger Subject: Re: [PATCH v2 07/19] KVM: arm64: vgic-its: Scope translation cache invalidations to an ITS In-Reply-To: <20240419223842.951452-8-oliver.upton@linux.dev> References: <20240419223842.951452-1-oliver.upton@linux.dev> <20240419223842.951452-8-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, eric.auger@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 19 Apr 2024 23:38:30 +0100, Oliver Upton wrote: > > As the current LPI translation cache is global, the corresponding > invalidation helpers are also globally-scoped. In anticipation of > constructing a translation cache per ITS, add a helper for scoped cache > invalidations. > > We still need to support global invalidations when LPIs are toggled on > a redistributor, as a property of the translation cache is that all > stored LPIs are known to be delieverable. > > Signed-off-by: Oliver Upton > --- > arch/arm64/kvm/vgic/vgic-its.c | 45 ++++++++++++++++++++++-------- > arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 +- > arch/arm64/kvm/vgic/vgic.h | 2 +- > 3 files changed, 35 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c > index 441134ad674e..4afd42b6a16c 100644 > --- a/arch/arm64/kvm/vgic/vgic-its.c > +++ b/arch/arm64/kvm/vgic/vgic-its.c > @@ -23,6 +23,8 @@ > #include "vgic.h" > #include "vgic-mmio.h" > > +static struct kvm_device_ops kvm_arm_vgic_its_ops; > + > static int vgic_its_save_tables_v0(struct vgic_its *its); > static int vgic_its_restore_tables_v0(struct vgic_its *its); > static int vgic_its_commit_v0(struct vgic_its *its); > @@ -616,7 +618,7 @@ static void vgic_its_cache_translation(struct kvm *kvm, struct vgic_its *its, > raw_spin_unlock_irqrestore(&dist->lpi_list_lock, flags); > } > > -void vgic_its_invalidate_cache(struct kvm *kvm) > +static void vgic_its_invalidate_cache(struct vgic_its *its) > { > struct vgic_dist *dist = &kvm->arch.vgic; Err. How does this work? Looks like you got the patch splitting wrong and that it doesn't bisect until patch #11. M. -- Without deviation from the norm, progress is not possible.