From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A69B747B for ; Fri, 14 Jul 2023 08:01:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 22AA2C433C7; Fri, 14 Jul 2023 08:01:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689321694; bh=UUYVzCsu67sjje2vM3O19o56+OOus48AI8DLYLauFT0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=LEHxieueHZCbC+nCJ8oUKjuUEap9aUUx/EwHTbWBxVilz08RWo5g2TXJ3XU5ScLzO rJ0+JWFfuoQNKXTs0ZXRuHuIeCClYwBi7M3hsz9Zc6cY37iU49wczUio/HSqyR1Is+ 7T4Rl/W+3VJtxMT2wh4Uv0qCk6K+biKe5cosK/89J4WovgQMQ+MlKLElnr3jiXxVn6 x//oRFlE2aEYH1C9+g8+nX6BKJ7QWbUybmDCc5joqrrksSvKL/qgslB57zasXcVQ2q 7Z/dMICGowyxw4XzhoXltxs8nwwsUguKt1gXC+yQZk3d7pOgXjBo3ICCVCaREp4wse JYYktJnYC3/ZQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qKDk3-00D1Zp-R7; Fri, 14 Jul 2023 09:01:31 +0100 Date: Fri, 14 Jul 2023 09:01:31 +0100 Message-ID: <86o7kevs4k.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, James Morse , Suzuki K Poulose , Zenghui Yu , Reiji Watanabe , rananta@google.com Subject: Re: [PATCH] KVM: arm64: Correctly handle RES0 bits PMEVTYPER_EL0.evtCount In-Reply-To: <20230713221649.3889210-1-oliver.upton@linux.dev> References: <20230713221649.3889210-1-oliver.upton@linux.dev> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, reijiw@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false AOn Thu, 13 Jul 2023 23:16:49 +0100, Oliver Upton wrote: > > The PMU event ID varies from 10 to 16 bits, depending on the PMU > version. If the PMU only supports 10 bits of event ID, bits [15:10] of > the evtCount field behave as RES0. > > While the actual PMU emulation code gets this right (i.e. RES0 bits are > masked out when programming the perf event), the sysreg emulation writes > an unmasked value to the in-memory cpu context. The net effect is that > guest reads and writes of PMEVTYPER_EL0 will see non-RES0 behavior in > the reserved bits of the field. > > As it so happens, kvm_pmu_set_counter_event_type() already writes a > masked value to the in-memory context that gets overwritten by > access_pmu_evtyper(). Fix the issue by removing the unnecessary (and > incorrect) register write in access_pmu_evtyper(). > > Signed-off-by: Oliver Upton Reviewed-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.