From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0542A20FE for ; Fri, 20 Jan 2023 14:04:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D037C4339B; Fri, 20 Jan 2023 14:04:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674223455; bh=RsGkcvnNtpSaNCyQB4mw8BBq8xS8J2zdcLN5ShvOTdE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=DpEKY2/CMiY/zNaitgj2T5rExEk/IURWoC0L6N4u+i3YdmqQjaup15yxRrMSC3NTz d3+3JKujvBW+BZWWIgtUJXM3daVozNzbNqaTmSWAv30ml5CIQpa+iTxbrhvPMvcCRp ClHmf2MpXFO5f8oCtd6YiJI9PkxTD6tJf8c79K7x/tbhLJchVQMm+zPaLLLEGTdHg5 pSIG9/YuSKCupTq6oMpqnJ5MS9AUb+xZvPmD6z2iFzkDhqmxMqftpZQSlzjmGPs/P/ L10MsLHQNFJywWVDbs+joNsYyGch0hKUCQg5P/PSp4yRrcOHGqqJBgt7HfovvP06PQ xYAUTOquA3tYw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pIs05-003Qff-7y; Fri, 20 Jan 2023 14:04:13 +0000 Date: Fri, 20 Jan 2023 14:04:12 +0000 Message-ID: <86o7qtmher.wl-maz@kernel.org> From: Marc Zyngier To: Reiji Watanabe Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v2 1/8] KVM: arm64: PMU: Have reset_pmu_reg() to clear a register In-Reply-To: <20230117013542.371944-2-reijiw@google.com> References: <20230117013542.371944-1-reijiw@google.com> <20230117013542.371944-2-reijiw@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: reijiw@google.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, pbonzini@redhat.com, ricarkol@google.com, oliver.upton@linux.dev, jingzhangos@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 17 Jan 2023 01:35:35 +0000, Reiji Watanabe wrote: > > On vCPU reset, PMCNTEN{SET,CLR}_EL0, PMINTEN{SET,CLR}_EL1, and > PMOVS{SET,CLR}_EL1 for a vCPU are reset by reset_pmu_reg(). > This function clears RAZ bits of those registers corresponding > to unimplemented event counters on the vCPU, and sets bits > corresponding to implemented event counters to a predefined > pseudo UNKNOWN value (some bits are set to 1). > > The function identifies (un)implemented event counters on the > vCPU based on the PMCR_EL1.N value on the host. Using the host > value for this would be problematic when KVM supports letting > userspace set PMCR_EL1.N to a value different from the host value > (some of the RAZ bits of those registers could end up being set to 1). > > Fix reset_pmu_reg() to clear the registers so that it can ensure > that all the RAZ bits are cleared even when the PMCR_EL1.N value > for the vCPU is different from the host value. > > Signed-off-by: Reiji Watanabe > --- > arch/arm64/kvm/sys_regs.c | 10 +--------- > 1 file changed, 1 insertion(+), 9 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index c6cbfe6b854b..ec4bdaf71a15 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -604,19 +604,11 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, > > static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > { > - u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); > - > /* No PMU available, any PMU reg may UNDEF... */ > if (!kvm_arm_support_pmu_v3()) > return; Is this still true? We remove the PMCR_EL0 access just below. > > - n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; > - n &= ARMV8_PMU_PMCR_N_MASK; > - if (n) > - mask |= GENMASK(n - 1, 0); > - > - reset_unknown(vcpu, r); > - __vcpu_sys_reg(vcpu, r->reg) &= mask; > + __vcpu_sys_reg(vcpu, r->reg) = 0; > } At the end of the day, this function has no dependency on the host at all, and only writes 0 to the per-vcpu register. So why not get rid of it altogether and have: diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c6cbfe6b854b..1d1514b89d75 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -976,7 +976,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } #define PMU_SYS_REG(r) \ - SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility + SYS_DESC(r), .visibility = pmu_visibility /* Macro to expand the PMEVCNTRn_EL0 register */ #define PMU_PMEVCNTR_EL0(n) \ which would fall-back the specified reset value (zero by default)? Thanks, M. -- Without deviation from the norm, progress is not possible. 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Fri, 20 Jan 2023 14:04:13 +0000 Date: Fri, 20 Jan 2023 14:04:12 +0000 Message-ID: <86o7qtmher.wl-maz@kernel.org> From: Marc Zyngier To: Reiji Watanabe Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v2 1/8] KVM: arm64: PMU: Have reset_pmu_reg() to clear a register In-Reply-To: <20230117013542.371944-2-reijiw@google.com> References: <20230117013542.371944-1-reijiw@google.com> <20230117013542.371944-2-reijiw@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: reijiw@google.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, pbonzini@redhat.com, ricarkol@google.com, oliver.upton@linux.dev, jingzhangos@google.com, rananta@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230120_060417_465986_9D5F6150 X-CRM114-Status: GOOD ( 30.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 17 Jan 2023 01:35:35 +0000, Reiji Watanabe wrote: > > On vCPU reset, PMCNTEN{SET,CLR}_EL0, PMINTEN{SET,CLR}_EL1, and > PMOVS{SET,CLR}_EL1 for a vCPU are reset by reset_pmu_reg(). > This function clears RAZ bits of those registers corresponding > to unimplemented event counters on the vCPU, and sets bits > corresponding to implemented event counters to a predefined > pseudo UNKNOWN value (some bits are set to 1). > > The function identifies (un)implemented event counters on the > vCPU based on the PMCR_EL1.N value on the host. Using the host > value for this would be problematic when KVM supports letting > userspace set PMCR_EL1.N to a value different from the host value > (some of the RAZ bits of those registers could end up being set to 1). > > Fix reset_pmu_reg() to clear the registers so that it can ensure > that all the RAZ bits are cleared even when the PMCR_EL1.N value > for the vCPU is different from the host value. > > Signed-off-by: Reiji Watanabe > --- > arch/arm64/kvm/sys_regs.c | 10 +--------- > 1 file changed, 1 insertion(+), 9 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index c6cbfe6b854b..ec4bdaf71a15 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -604,19 +604,11 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, > > static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > { > - u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); > - > /* No PMU available, any PMU reg may UNDEF... */ > if (!kvm_arm_support_pmu_v3()) > return; Is this still true? We remove the PMCR_EL0 access just below. > > - n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; > - n &= ARMV8_PMU_PMCR_N_MASK; > - if (n) > - mask |= GENMASK(n - 1, 0); > - > - reset_unknown(vcpu, r); > - __vcpu_sys_reg(vcpu, r->reg) &= mask; > + __vcpu_sys_reg(vcpu, r->reg) = 0; > } At the end of the day, this function has no dependency on the host at all, and only writes 0 to the per-vcpu register. So why not get rid of it altogether and have: diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c6cbfe6b854b..1d1514b89d75 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -976,7 +976,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } #define PMU_SYS_REG(r) \ - SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility + SYS_DESC(r), .visibility = pmu_visibility /* Macro to expand the PMEVCNTRn_EL0 register */ #define PMU_PMEVCNTR_EL0(n) \ which would fall-back the specified reset value (zero by default)? Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel