From: Marc Zyngier <maz@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: tglx@linutronix.de, jason@lakedaemon.net, ralf@linux-mips.org,
paul.burton@mips.com, jhogan@kernel.org, robh+dt@kernel.org,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, mark.rutland@arm.com,
john@phrozen.org, Hauke Mehrtens <hauke@hauke-m.de>
Subject: Re: [PATCH 3/5] MIPS: lantiq: add an irq_domain and irq_chip for EBU
Date: Sat, 03 Aug 2019 10:12:49 +0100 [thread overview]
Message-ID: <86o916mx2m.wl-maz@kernel.org> (raw)
In-Reply-To: <CAFBinCCb4aTfuxaSrUp8xbUjjefi_qHOUJLjzH+acUTLY+6Geg@mail.gmail.com>
Hi Martin,
On Thu, 01 Aug 2019 18:42:42 +0100,
Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
[...]
> > > +static void ltq_ebu_irq_handler(struct irq_desc *desc)
> > > +{
> > > + struct irq_domain *domain = irq_desc_get_handler_data(desc);
> > > + struct irq_chip *irqchip = irq_desc_get_chip(desc);
> > > +
> > > + chained_irq_enter(irqchip, desc);
> > > +
> > > + generic_handle_irq(irq_find_mapping(domain, 0));
> >
> > Having an irqdomain for a single interrupt is a bit over the top... Is
> > that for the convenience of the DT infrastructure?
> yes, I did it to get DT support
> please let me know if there's a "better" way (preferably with another
> driver as example)
To be honest, the chained handler is what troubles me the most. You
normally would use such a construct if you had a multiplexer. In your
case, you have a 1:1 relationship between input and output. It is just
that this irqchip allows the trigger to be adapted, which normally
calls for a hierarchical implementation.
In your case, with only a single interrupt, it doesn't matter much
though.
>
> [...]
> > > + irq_create_mapping(domain, 0);
> >
> > Why do you need to perform this eagerly? I'd expect this interrupt to
> > be mapped when it is actually claimed by a driver.
> I don't remember why I added it, it may be left-over from copying from
> another driver
> in v2 I'll try to drop it
>
> > > +
> > > + irq_set_chained_handler_and_data(irq, ltq_ebu_irq_handler, domain);
> >
> > And there is no HW initialisation whatsoever? I'd expect, at the very
> > least, the sole interrupt to be configured as disabled/masked.
> I can add that. is there any "best practice" on what I should
> initialize (just disable it or also set a "default" mode like
> LEVEL_LOW)?
Whichever default state makes sense. What you want to avoid is to boot
the kernel with a screaming interrupt because some firmware has left
it enabled.
Thanks,
M.
--
Jazz is not dead, it just smells funny.
next prev parent reply other threads:[~2019-08-03 9:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-27 17:53 [PATCH 0/5] MIPS: lantiq: EBU interrupt controller and generalization Martin Blumenstingl
2019-07-27 17:53 ` [PATCH 1/5] dt-bindings: MIPS: lantiq: Add documentation for the External Bus Unit Martin Blumenstingl
2019-07-29 23:17 ` Rob Herring
2019-07-27 17:53 ` [PATCH 2/5] MIPS: lantiq: use a generic "EBU" driver for Falcon and XWAY SoCs Martin Blumenstingl
2019-07-27 18:35 ` John Crispin
2019-07-27 18:37 ` Martin Blumenstingl
2019-07-27 17:53 ` [PATCH 3/5] MIPS: lantiq: add an irq_domain and irq_chip for EBU Martin Blumenstingl
2019-07-28 10:01 ` Marc Zyngier
2019-08-01 17:42 ` Martin Blumenstingl
2019-08-03 9:12 ` Marc Zyngier [this message]
2019-08-03 17:33 ` Martin Blumenstingl
2019-08-05 15:03 ` Marc Zyngier
2019-07-27 17:53 ` [PATCH 4/5] MIPS: dts: lantiq: danube: mark the ebu0 node as interrupt-controller Martin Blumenstingl
2019-07-27 17:53 ` [PATCH 5/5] MIPS: dts: lantiq: danube: easy50712: route the PCI_INTA IRQ through EBU Martin Blumenstingl
2019-07-28 10:03 ` Marc Zyngier
2019-07-29 21:55 ` Hauke Mehrtens
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