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From: Torbjorn Granlund <tg@gmplib.org>
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Date: Tue, 07 May 2013 21:30:24 +0200
In-Reply-To: <8638typsnp.fsf@shell.gmplib.org> (Torbjorn Granlund's message of
	"Tue\, 07 May 2013 20\:10\:50 +0200")
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Subject: Re: [Qemu-devel] [Qemu-ppc] Incorrect handling of more PPC64 insns
	(PATCH)
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To: Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson <rth@twiddle.net>

I realised a possible problem with my suggested patch.

What about a 32-bit processor?  Then NARROW_MODE macro is identical 0.

The pre-patch behaviour was then to ignore the L bit and decode both
32-bit and 64-bit instruction in the same way.

Apparently that is correct behaviour.  (The manual is slightly vague,
but I let hardware decide.)

With my patch, the bit is not ignored, and invalid code will be
generated for 32-bit targets, if they'd set the L bit.

Here is an uglier but hopefully completely correct patch.

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1a84653..69d684c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -675,49 +675,65 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCG=
v reg)
 /* cmp */
 static void gen_cmp(DisasContext *ctx)
 {
-    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
+#if defined(TARGET_PPC64)
+    if (!(ctx->opcode & 0x00200000)) {
+#endif
         gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                      1, crfD(ctx->opcode));
+#if defined(TARGET_PPC64)
     } else {
         gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                    1, crfD(ctx->opcode));
     }
+#endif
 }
=20
 /* cmpi */
 static void gen_cmpi(DisasContext *ctx)
 {
-    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
+#if defined(TARGET_PPC64)
+    if (!(ctx->opcode & 0x00200000)) {
+#endif
         gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
                       1, crfD(ctx->opcode));
+#if defined(TARGET_PPC64)
     } else {
         gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
                     1, crfD(ctx->opcode));
     }
+#endif
 }
=20
 /* cmpl */
 static void gen_cmpl(DisasContext *ctx)
 {
-    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
+#if defined(TARGET_PPC64)
+    if (!(ctx->opcode & 0x00200000)) {
+#endif
         gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                      0, crfD(ctx->opcode));
+#if defined(TARGET_PPC64)
     } else {
         gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
                    0, crfD(ctx->opcode));
     }
+#endif
 }
=20
 /* cmpli */
 static void gen_cmpli(DisasContext *ctx)
 {
-    if (NARROW_MODE(ctx) || !(ctx->opcode & 0x00200000)) {
+#if defined(TARGET_PPC64)
+    if (!(ctx->opcode & 0x00200000)) {
+#endif
         gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
                       0, crfD(ctx->opcode));
+#if defined(TARGET_PPC64)
     } else {
         gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
                     0, crfD(ctx->opcode));
     }
+#endif
 }
=20
 /* isel (PowerPC 2.03 specification) */

--=20
Torbj=C3=B6rn