From: Marc Zyngier <maz@kernel.org>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
"Toan Le" <toan@os.amperecomputing.com>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Thomas Gleixner" <tglx@linutronix.de>
Subject: Re: [PATCH 09/12] PCI: xgene-msi: Sanitise MSI allocation and affinity setting
Date: Tue, 08 Jul 2025 15:41:01 +0100 [thread overview]
Message-ID: <86qzyqagoy.wl-maz@kernel.org> (raw)
In-Reply-To: <aGvga+1Q6SOsTScK@lpieralisi>
On Mon, 07 Jul 2025 15:57:47 +0100,
Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
>
> On Sat, Jun 28, 2025 at 06:30:02PM +0100, Marc Zyngier wrote:
[...]
> > + * Effectively, this amounts to:
> > + * - hwirq[7]::cpu[2:0] is the target frame number
> > + * - hwirq[6:4] is the register index in any given frame
> > + * - hwirq[3:0] is the MSI data
>
> I think that adding macros to define these subfields shifts would simplify
> reading and reviewing the code - while reviewing xgene_msi_isr() I
> realized it is hard to understand where the shifts to pack/unpack hwirq come
> from. I'd understand you don't want to use FIELD_PREP/GET on hwirq, it
> is not a HW field but rather a SW encoding you created but at least defining
> the shifts and using them throughout would help.
I have no problem using FIELD_*() for that. I've now reworked this to
make it clearer as well as added a bit more documentation on the
behaviour of the MSInRx registers (they are quite funky).
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-07-08 14:45 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-28 17:29 [PATCH 00/12] PCI: xgene: Fix and simplify the MSI driver Marc Zyngier
2025-06-28 17:29 ` [PATCH 01/12] genirq: Teach handle_simple_irq() to resend an in-progress interrupt Marc Zyngier
2025-07-03 16:29 ` Thomas Gleixner
2025-06-28 17:29 ` [PATCH 02/12] PCI: xgene: Defer probing if the MSI widget driver hasn't probed yet Marc Zyngier
2025-06-28 17:29 ` [PATCH 03/12] PCI: xgene: Drop useless conditional compilation Marc Zyngier
2025-06-28 17:29 ` [PATCH 04/12] PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKN Marc Zyngier
2025-06-28 17:29 ` [PATCH 05/12] PCI: xgene-msi: Make per-CPU interrupt setup robust Marc Zyngier
2025-06-28 17:29 ` [PATCH 06/12] PCI: xgene-msi: Drop superfluous fields from xgene_msi structure Marc Zyngier
2025-06-28 17:30 ` [PATCH 07/12] PCI: xgene-msi: Use device-managed memory allocations Marc Zyngier
2025-06-28 17:30 ` [PATCH 08/12] PCI: xgene-msi: Get rid of intermediate tracking structure Marc Zyngier
2025-07-07 15:22 ` Lorenzo Pieralisi
2025-07-08 14:46 ` Marc Zyngier
2025-06-28 17:30 ` [PATCH 09/12] PCI: xgene-msi: Sanitise MSI allocation and affinity setting Marc Zyngier
2025-07-07 14:57 ` Lorenzo Pieralisi
2025-07-08 14:41 ` Marc Zyngier [this message]
2025-06-28 17:30 ` [PATCH 10/12] PCI: xgene-msi: Resend an MSI racing with itself on a different CPU Marc Zyngier
2025-06-28 17:30 ` [PATCH 11/12] PCI: xgene-msi: Probe as a standard platform driver Marc Zyngier
2025-06-28 17:30 ` [PATCH 12/12] PCI: xgene-msi: Restructure handler setup/teardown Marc Zyngier
2025-07-07 11:14 ` Lorenzo Pieralisi
2025-07-07 15:58 ` Marc Zyngier
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