[Qemu-devel] [PATCH v2 2/2] openpic: Reset IRQ source private members

[Paul Janzen <pcj@pauljanzen.org>]

The openpic emulation code maintains an allowable-CPU's bitmap
("destmask") for each IRQ source which is calculated from the IDR
register value whenever the guest OS writes to it.  However, if the
guest OS relies on the system to set the IDR register to a default
value at reset, and does not write IDR, then destmask does not get
updated, and interrupts do not get propagated to the guest.
Additionally, if an IRQ source is marked as critical, the source's
internal "output" and "nomask" fields are not correctly reset when the
PIC is reset.

Fix both these issues by calling write_IRQreg_idr from within
openpic_reset, instead of simply setting the IDR register to the
specified idr_reset value.

Signed-off-by: Paul Janzen <pcj@pauljanzen.org>
---
 hw/intc/openpic.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 81469ff..811db6f 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -1435,8 +1435,6 @@ static void openpic_reset(DeviceState *d)
     /* Initialise IRQ sources */
     for (i = 0; i < opp->max_irq; i++) {
         opp->src[i].ivpr = opp->ivpr_reset;
-        opp->src[i].idr  = opp->idr_reset;
-
         switch (opp->src[i].type) {
         case IRQ_TYPE_NORMAL:
             opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK);
@@ -1449,6 +1447,8 @@ static void openpic_reset(DeviceState *d)
         case IRQ_TYPE_FSLSPECIAL:
             break;
         }
+
+        write_IRQreg_idr(opp, i, opp->idr_reset);
     }
     /* Initialise IRQ destinations */
     for (i = 0; i < MAX_CPU; i++) {
-- 
1.7.1