From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02D3EC3DA7D for ; Thu, 5 Jan 2023 14:23:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231431AbjAEOWr (ORCPT ); Thu, 5 Jan 2023 09:22:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233077AbjAEOWZ (ORCPT ); Thu, 5 Jan 2023 09:22:25 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 740C644C76; Thu, 5 Jan 2023 06:22:24 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 2C1E8B81AE6; Thu, 5 Jan 2023 14:22:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9CE7C433EF; Thu, 5 Jan 2023 14:22:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672928541; bh=CGd0JdacF6pHnwbp0w0jPBNen22NaJhE2zmyCL4nB+E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=a/i+eCP2jEIXfdvnROL5C/JRloqbsMH/h49y/qL8zjBr0gAbp5LjafKlMU9Kv04d8 DAKhcgaUeMKEv7z2xZuWTyha6+qsVCrbqHGyqboTr6cwt/fsoHiDujl6FH2gwwekhL Ax4CvwpC+0wi9NE6eVo6gBH8fBBgbZkN+hS59DuZC5OUp6PAUYxVJed2IIEFLsJQkH Wwi2qGXhpj3sUnjfCX+pxTepAzxfkS2TSpa9rAEiaASYjjo9oB4kTVWYdXpeCU38l8 ATaawivr9vanDcka5ByHWdSOBUExJb0xpOqkZZNtG6VKasXKISCxIW8w+RhdrRYPpM vT27RVbNG1l2A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pDR8N-00H107-Fi; Thu, 05 Jan 2023 14:22:19 +0000 Date: Thu, 05 Jan 2023 14:22:07 +0000 Message-ID: <86sfgpnjsg.wl-maz@kernel.org> From: Marc Zyngier To: Yogesh Lal Cc: , , , , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" Subject: Re: ERRATUM_858921 is broken on 5.15 kernel In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: quic_ylal@quicinc.com, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, 05 Jan 2023 13:33:48 +0000, Yogesh Lal wrote: >=20 > Hi, >=20 > We are observing issue on A73 core where ERRATUM_858921 is broken. >=20 > On 5.15 kernel arch_timer_enable_workaround is set by reading > arm64_858921_read_cntpct_el0 and arm64_858921_read_cntvct_el0 during > timer register using following path. Have you checked whether the issue is still present on 6.1? >=20 > arch_timer_enable_workaround->atomic_set(&timer_unstable_counter_workarou= nd_in_use, > 1); >=20 > [code snap] > 564 static > 565 void arch_timer_enable_workaround(const struct > arch_timer_erratum_workaround *wa, > 566=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool local) > 567 { > 568=C2=A0=C2=A0=C2=A0=C2=A0 int i; > 569 > 570=C2=A0=C2=A0=C2=A0=C2=A0 if (local) { > 571 __this_cpu_write(timer_unstable_counter_workaround, wa); > 572=C2=A0=C2=A0=C2=A0=C2=A0 } else { > 573=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 for_each_possible_cpu(i) > 574=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 per_cpu(timer_unstable_= counter_workaround, i) =3D wa; > 575=C2=A0=C2=A0=C2=A0=C2=A0 } > 576 > 577=C2=A0=C2=A0=C2=A0=C2=A0 if (wa->read_cntvct_el0 || wa->read_cntpct_el= 0) > 578 atomic_set(&timer_unstable_counter_workaround_in_use, 1); >=20 >=20 > and based on above workaround enablement , appropriate function to get > counter is used. >=20 > 1008 static void __init arch_counter_register(unsigned type) > 1009 { > 1010=C2=A0=C2=A0=C2=A0=C2=A0 u64 start_count; > 1011 > 1012=C2=A0=C2=A0=C2=A0=C2=A0 /* Register the CP15 based counter if we hav= e one */ > 1013=C2=A0=C2=A0=C2=A0=C2=A0 if (type & ARCH_TIMER_TYPE_CP15) { > 1014=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u64 (*rd)(void); > 1015 > 1016=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if ((IS_ENABLED(CONF= IG_ARM64) && !is_hyp_mode_available()) || > 1017=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) { > 1018=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 if (arch_timer_counter_has_wa()) > 1019=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntvct_stable; > 1020=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 else > 1021=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntvct; > 1022=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } else { > 1023=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 if (arch_timer_counter_has_wa()) > 1024=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntpct_stable; > 1025=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 else > 1026=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 rd =3D arch_counter_get_cntpct; > 1027=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > [snap] > 1043 =C2=A0=C2=A0=C2=A0 /* 56 bits minimum, so we assume worst case rollo= ver */ > 1044 =C2=A0=C2=A0=C2=A0 sched_clock_register(arch_timer_read_counter, 56,= arch_timer_rate); >=20 >=20 > As our boot cores are not impacted by errata sched_clock_register() > will register !arch_timer_counter_has_wa() callback. >=20 > Now when errata impacted core boots up and sched_clock_register > already register will !arch_timer_counter_has_wa() path. > As sched_clock_register is not per_cpu bases so > arch_timer_read_counter will always point to > !arch_timer_counter_has_wa() function calls. Please try the following hack, only compile tested as I do not have access to any affected HW, and report whether this solves your issue or not. Note that this is based on 6.2-rc2. Thanks, M. diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm= _arch_timer.c index e09d4427f604..a7cf0a2c86d3 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -230,6 +230,28 @@ static u64 arch_counter_read_cc(const struct cyclecoun= ter *cc) return arch_timer_read_counter(); } =20 +static bool arch_timer_counter_has_wa(void); + +static u64 (*arch_counter_get_read_fn(void))(void) +{ + u64 (*rd)(void); + + if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || + arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) { + if (arch_timer_counter_has_wa()) + rd =3D arch_counter_get_cntvct_stable; + else + rd =3D arch_counter_get_cntvct; + } else { + if (arch_timer_counter_has_wa()) + rd =3D arch_counter_get_cntpct_stable; + else + rd =3D arch_counter_get_cntpct; + } + + return rd; +} + static struct clocksource clocksource_counter =3D { .name =3D "arch_sys_counter", .id =3D CSID_ARM_ARCH_COUNTER, @@ -571,8 +593,10 @@ void arch_timer_enable_workaround(const struct arch_ti= mer_erratum_workaround *wa per_cpu(timer_unstable_counter_workaround, i) =3D wa; } =20 - if (wa->read_cntvct_el0 || wa->read_cntpct_el0) + if (wa->read_cntvct_el0 || wa->read_cntpct_el0) { atomic_set(&timer_unstable_counter_workaround_in_use, 1); + arch_timer_read_counter =3D arch_counter_get_read_fn(); + } =20 /* * Don't use the vdso fastpath if errata require using the @@ -641,7 +665,7 @@ static bool arch_timer_counter_has_wa(void) #else #define arch_timer_check_ool_workaround(t,a) do { } while(0) #define arch_timer_this_cpu_has_cntvct_wa() ({false;}) -#define arch_timer_counter_has_wa() ({false;}) +static bool arch_timer_counter_has_wa(void) { return false; } #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */ =20 static __always_inline irqreturn_t timer_handler(const int access, @@ -1079,22 +1103,7 @@ static void __init arch_counter_register(unsigned ty= pe) =20 /* Register the CP15 based counter if we have one */ if (type & ARCH_TIMER_TYPE_CP15) { - u64 (*rd)(void); - - if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || - arch_timer_uses_ppi =3D=3D ARCH_TIMER_VIRT_PPI) { - if (arch_timer_counter_has_wa()) - rd =3D arch_counter_get_cntvct_stable; - else - rd =3D arch_counter_get_cntvct; - } else { - if (arch_timer_counter_has_wa()) - rd =3D arch_counter_get_cntpct_stable; - else - rd =3D arch_counter_get_cntpct; - } - - arch_timer_read_counter =3D rd; + arch_timer_read_counter =3D arch_counter_get_read_fn(); clocksource_counter.vdso_clock_mode =3D vdso_default; } else { arch_timer_read_counter =3D arch_counter_get_cntvct_mem; --=20 Without deviation from the norm, progress is not possible. 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"linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" Subject: Re: ERRATUM_858921 is broken on 5.15 kernel In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: quic_ylal@quicinc.com, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230105_142220_641730_74C29F7C X-CRM114-Status: GOOD ( 30.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCAwNSBKYW4gMjAyMyAxMzozMzo0OCArMDAwMCwKWW9nZXNoIExhbCA8cXVpY195bGFs QHF1aWNpbmMuY29tPiB3cm90ZToKPiAKPiBIaSwKPiAKPiBXZSBhcmUgb2JzZXJ2aW5nIGlzc3Vl IG9uIEE3MyBjb3JlIHdoZXJlIEVSUkFUVU1fODU4OTIxIGlzIGJyb2tlbi4KPiAKPiBPbiA1LjE1 IGtlcm5lbCBhcmNoX3RpbWVyX2VuYWJsZV93b3JrYXJvdW5kIGlzIHNldCBieSByZWFkaW5nCj4g YXJtNjRfODU4OTIxX3JlYWRfY250cGN0X2VsMCBhbmQgYXJtNjRfODU4OTIxX3JlYWRfY250dmN0 X2VsMCBkdXJpbmcKPiB0aW1lciByZWdpc3RlciB1c2luZyBmb2xsb3dpbmcgcGF0aC4KCkhhdmUg eW91IGNoZWNrZWQgd2hldGhlciB0aGUgaXNzdWUgaXMgc3RpbGwgcHJlc2VudCBvbiA2LjE/Cgo+ IAo+IGFyY2hfdGltZXJfZW5hYmxlX3dvcmthcm91bmQtPmF0b21pY19zZXQoJnRpbWVyX3Vuc3Rh YmxlX2NvdW50ZXJfd29ya2Fyb3VuZF9pbl91c2UsCj4gMSk7Cj4gCj4gW2NvZGUgc25hcF0KPiA1 NjQgc3RhdGljCj4gNTY1IHZvaWQgYXJjaF90aW1lcl9lbmFibGVfd29ya2Fyb3VuZChjb25zdCBz dHJ1Y3QKPiBhcmNoX3RpbWVyX2VycmF0dW1fd29ya2Fyb3VuZCAqd2EsCj4gNTY2wqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGJvb2wg bG9jYWwpCj4gNTY3IHsKPiA1NjjCoMKgwqDCoCBpbnQgaTsKPiA1NjkKPiA1NzDCoMKgwqDCoCBp ZiAobG9jYWwpIHsKPiA1NzEgX190aGlzX2NwdV93cml0ZSh0aW1lcl91bnN0YWJsZV9jb3VudGVy X3dvcmthcm91bmQsIHdhKTsKPiA1NzLCoMKgwqDCoCB9IGVsc2Ugewo+IDU3M8KgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoCBmb3JfZWFjaF9wb3NzaWJsZV9jcHUoaSkKPiA1NzTCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHBlcl9jcHUodGltZXJfdW5zdGFibGVfY291bnRl cl93b3JrYXJvdW5kLCBpKSA9IHdhOwo+IDU3NcKgwqDCoMKgIH0KPiA1NzYKPiA1NzfCoMKgwqDC oCBpZiAod2EtPnJlYWRfY250dmN0X2VsMCB8fCB3YS0+cmVhZF9jbnRwY3RfZWwwKQo+IDU3OCBh dG9taWNfc2V0KCZ0aW1lcl91bnN0YWJsZV9jb3VudGVyX3dvcmthcm91bmRfaW5fdXNlLCAxKTsK PiAKPiAKPiBhbmQgYmFzZWQgb24gYWJvdmUgd29ya2Fyb3VuZCBlbmFibGVtZW50ICwgYXBwcm9w cmlhdGUgZnVuY3Rpb24gdG8gZ2V0Cj4gY291bnRlciBpcyB1c2VkLgo+IAo+IDEwMDggc3RhdGlj IHZvaWQgX19pbml0IGFyY2hfY291bnRlcl9yZWdpc3Rlcih1bnNpZ25lZCB0eXBlKQo+IDEwMDkg ewo+IDEwMTDCoMKgwqDCoCB1NjQgc3RhcnRfY291bnQ7Cj4gMTAxMQo+IDEwMTLCoMKgwqDCoCAv KiBSZWdpc3RlciB0aGUgQ1AxNSBiYXNlZCBjb3VudGVyIGlmIHdlIGhhdmUgb25lICovCj4gMTAx M8KgwqDCoMKgIGlmICh0eXBlICYgQVJDSF9USU1FUl9UWVBFX0NQMTUpIHsKPiAxMDE0wqDCoMKg wqDCoMKgwqDCoCB1NjQgKCpyZCkodm9pZCk7Cj4gMTAxNQo+IDEwMTbCoMKgwqDCoMKgwqDCoMKg IGlmICgoSVNfRU5BQkxFRChDT05GSUdfQVJNNjQpICYmICFpc19oeXBfbW9kZV9hdmFpbGFibGUo KSkgfHwKPiAxMDE3wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGFyY2hfdGltZXJfdXNlc19wcGkg PT0gQVJDSF9USU1FUl9WSVJUX1BQSSkgewo+IDEwMTjCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAg aWYgKGFyY2hfdGltZXJfY291bnRlcl9oYXNfd2EoKSkKPiAxMDE5wqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgwqAgcmQgPSBhcmNoX2NvdW50ZXJfZ2V0X2NudHZjdF9zdGFibGU7Cj4gMTAy MMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBlbHNlCj4gMTAyMcKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgwqDCoMKgIHJkID0gYXJjaF9jb3VudGVyX2dldF9jbnR2Y3Q7Cj4gMTAyMsKgwqDCoMKg wqDCoMKgwqAgfSBlbHNlIHsKPiAxMDIzwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIGlmIChhcmNo X3RpbWVyX2NvdW50ZXJfaGFzX3dhKCkpCj4gMTAyNMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoMKgIHJkID0gYXJjaF9jb3VudGVyX2dldF9jbnRwY3Rfc3RhYmxlOwo+IDEwMjXCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqAgZWxzZQo+IDEwMjbCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKg wqDCoCByZCA9IGFyY2hfY291bnRlcl9nZXRfY250cGN0Owo+IDEwMjfCoMKgwqDCoMKgwqDCoMKg IH0KPiBbc25hcF0KPiAxMDQzIMKgwqDCoCAvKiA1NiBiaXRzIG1pbmltdW0sIHNvIHdlIGFzc3Vt ZSB3b3JzdCBjYXNlIHJvbGxvdmVyICovCj4gMTA0NCDCoMKgwqAgc2NoZWRfY2xvY2tfcmVnaXN0 ZXIoYXJjaF90aW1lcl9yZWFkX2NvdW50ZXIsIDU2LCBhcmNoX3RpbWVyX3JhdGUpOwo+IAo+IAo+ IEFzIG91ciBib290IGNvcmVzIGFyZSBub3QgaW1wYWN0ZWQgYnkgZXJyYXRhIHNjaGVkX2Nsb2Nr X3JlZ2lzdGVyKCkKPiB3aWxsIHJlZ2lzdGVyICFhcmNoX3RpbWVyX2NvdW50ZXJfaGFzX3dhKCkg Y2FsbGJhY2suCj4gCj4gTm93IHdoZW4gZXJyYXRhIGltcGFjdGVkIGNvcmUgYm9vdHMgdXAgYW5k IHNjaGVkX2Nsb2NrX3JlZ2lzdGVyCj4gYWxyZWFkeSByZWdpc3RlciB3aWxsICFhcmNoX3RpbWVy X2NvdW50ZXJfaGFzX3dhKCkgcGF0aC4KPiBBcyBzY2hlZF9jbG9ja19yZWdpc3RlciBpcyBub3Qg cGVyX2NwdSBiYXNlcyBzbwo+IGFyY2hfdGltZXJfcmVhZF9jb3VudGVyIHdpbGwgYWx3YXlzIHBv aW50IHRvCj4gIWFyY2hfdGltZXJfY291bnRlcl9oYXNfd2EoKSBmdW5jdGlvbiBjYWxscy4KClBs ZWFzZSB0cnkgdGhlIGZvbGxvd2luZyBoYWNrLCBvbmx5IGNvbXBpbGUgdGVzdGVkIGFzIEkgZG8g bm90IGhhdmUKYWNjZXNzIHRvIGFueSBhZmZlY3RlZCBIVywgYW5kIHJlcG9ydCB3aGV0aGVyIHRo aXMgc29sdmVzIHlvdXIgaXNzdWUKb3Igbm90LiBOb3RlIHRoYXQgdGhpcyBpcyBiYXNlZCBvbiA2 LjItcmMyLgoKVGhhbmtzLAoKCU0uCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9jbG9ja3NvdXJjZS9h cm1fYXJjaF90aW1lci5jIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9hcm1fYXJjaF90aW1lci5jCmlu ZGV4IGUwOWQ0NDI3ZjYwNC4uYTdjZjBhMmM4NmQzIDEwMDY0NAotLS0gYS9kcml2ZXJzL2Nsb2Nr c291cmNlL2FybV9hcmNoX3RpbWVyLmMKKysrIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9hcm1fYXJj aF90aW1lci5jCkBAIC0yMzAsNiArMjMwLDI4IEBAIHN0YXRpYyB1NjQgYXJjaF9jb3VudGVyX3Jl YWRfY2MoY29uc3Qgc3RydWN0IGN5Y2xlY291bnRlciAqY2MpCiAJcmV0dXJuIGFyY2hfdGltZXJf cmVhZF9jb3VudGVyKCk7CiB9CiAKK3N0YXRpYyBib29sIGFyY2hfdGltZXJfY291bnRlcl9oYXNf d2Eodm9pZCk7CisKK3N0YXRpYyB1NjQgKCphcmNoX2NvdW50ZXJfZ2V0X3JlYWRfZm4odm9pZCkp KHZvaWQpCit7CisJdTY0ICgqcmQpKHZvaWQpOworCisJaWYgKChJU19FTkFCTEVEKENPTkZJR19B Uk02NCkgJiYgIWlzX2h5cF9tb2RlX2F2YWlsYWJsZSgpKSB8fAorCSAgICBhcmNoX3RpbWVyX3Vz ZXNfcHBpID09IEFSQ0hfVElNRVJfVklSVF9QUEkpIHsKKwkJaWYgKGFyY2hfdGltZXJfY291bnRl cl9oYXNfd2EoKSkKKwkJCXJkID0gYXJjaF9jb3VudGVyX2dldF9jbnR2Y3Rfc3RhYmxlOworCQll bHNlCisJCQlyZCA9IGFyY2hfY291bnRlcl9nZXRfY250dmN0OworCX0gZWxzZSB7CisJCWlmIChh cmNoX3RpbWVyX2NvdW50ZXJfaGFzX3dhKCkpCisJCQlyZCA9IGFyY2hfY291bnRlcl9nZXRfY250 cGN0X3N0YWJsZTsKKwkJZWxzZQorCQkJcmQgPSBhcmNoX2NvdW50ZXJfZ2V0X2NudHBjdDsKKwl9 CisKKwlyZXR1cm4gcmQ7Cit9CisKIHN0YXRpYyBzdHJ1Y3QgY2xvY2tzb3VyY2UgY2xvY2tzb3Vy Y2VfY291bnRlciA9IHsKIAkubmFtZQk9ICJhcmNoX3N5c19jb3VudGVyIiwKIAkuaWQJPSBDU0lE X0FSTV9BUkNIX0NPVU5URVIsCkBAIC01NzEsOCArNTkzLDEwIEBAIHZvaWQgYXJjaF90aW1lcl9l bmFibGVfd29ya2Fyb3VuZChjb25zdCBzdHJ1Y3QgYXJjaF90aW1lcl9lcnJhdHVtX3dvcmthcm91 bmQgKndhCiAJCQlwZXJfY3B1KHRpbWVyX3Vuc3RhYmxlX2NvdW50ZXJfd29ya2Fyb3VuZCwgaSkg PSB3YTsKIAl9CiAKLQlpZiAod2EtPnJlYWRfY250dmN0X2VsMCB8fCB3YS0+cmVhZF9jbnRwY3Rf ZWwwKQorCWlmICh3YS0+cmVhZF9jbnR2Y3RfZWwwIHx8IHdhLT5yZWFkX2NudHBjdF9lbDApIHsK IAkJYXRvbWljX3NldCgmdGltZXJfdW5zdGFibGVfY291bnRlcl93b3JrYXJvdW5kX2luX3VzZSwg MSk7CisJCWFyY2hfdGltZXJfcmVhZF9jb3VudGVyID0gYXJjaF9jb3VudGVyX2dldF9yZWFkX2Zu KCk7CisJfQogCiAJLyoKIAkgKiBEb24ndCB1c2UgdGhlIHZkc28gZmFzdHBhdGggaWYgZXJyYXRh IHJlcXVpcmUgdXNpbmcgdGhlCkBAIC02NDEsNyArNjY1LDcgQEAgc3RhdGljIGJvb2wgYXJjaF90 aW1lcl9jb3VudGVyX2hhc193YSh2b2lkKQogI2Vsc2UKICNkZWZpbmUgYXJjaF90aW1lcl9jaGVj a19vb2xfd29ya2Fyb3VuZCh0LGEpCQlkbyB7IH0gd2hpbGUoMCkKICNkZWZpbmUgYXJjaF90aW1l cl90aGlzX2NwdV9oYXNfY250dmN0X3dhKCkJCSh7ZmFsc2U7fSkKLSNkZWZpbmUgYXJjaF90aW1l cl9jb3VudGVyX2hhc193YSgpCQkJKHtmYWxzZTt9KQorc3RhdGljIGJvb2wgYXJjaF90aW1lcl9j b3VudGVyX2hhc193YSh2b2lkKQkJeyByZXR1cm4gZmFsc2U7IH0KICNlbmRpZiAvKiBDT05GSUdf QVJNX0FSQ0hfVElNRVJfT09MX1dPUktBUk9VTkQgKi8KIAogc3RhdGljIF9fYWx3YXlzX2lubGlu ZSBpcnFyZXR1cm5fdCB0aW1lcl9oYW5kbGVyKGNvbnN0IGludCBhY2Nlc3MsCkBAIC0xMDc5LDIy ICsxMTAzLDcgQEAgc3RhdGljIHZvaWQgX19pbml0IGFyY2hfY291bnRlcl9yZWdpc3Rlcih1bnNp Z25lZCB0eXBlKQogCiAJLyogUmVnaXN0ZXIgdGhlIENQMTUgYmFzZWQgY291bnRlciBpZiB3ZSBo YXZlIG9uZSAqLwogCWlmICh0eXBlICYgQVJDSF9USU1FUl9UWVBFX0NQMTUpIHsKLQkJdTY0ICgq cmQpKHZvaWQpOwotCi0JCWlmICgoSVNfRU5BQkxFRChDT05GSUdfQVJNNjQpICYmICFpc19oeXBf bW9kZV9hdmFpbGFibGUoKSkgfHwKLQkJICAgIGFyY2hfdGltZXJfdXNlc19wcGkgPT0gQVJDSF9U SU1FUl9WSVJUX1BQSSkgewotCQkJaWYgKGFyY2hfdGltZXJfY291bnRlcl9oYXNfd2EoKSkKLQkJ CQlyZCA9IGFyY2hfY291bnRlcl9nZXRfY250dmN0X3N0YWJsZTsKLQkJCWVsc2UKLQkJCQlyZCA9 IGFyY2hfY291bnRlcl9nZXRfY250dmN0OwotCQl9IGVsc2UgewotCQkJaWYgKGFyY2hfdGltZXJf Y291bnRlcl9oYXNfd2EoKSkKLQkJCQlyZCA9IGFyY2hfY291bnRlcl9nZXRfY250cGN0X3N0YWJs ZTsKLQkJCWVsc2UKLQkJCQlyZCA9IGFyY2hfY291bnRlcl9nZXRfY250cGN0OwotCQl9Ci0KLQkJ YXJjaF90aW1lcl9yZWFkX2NvdW50ZXIgPSByZDsKKwkJYXJjaF90aW1lcl9yZWFkX2NvdW50ZXIg PSBhcmNoX2NvdW50ZXJfZ2V0X3JlYWRfZm4oKTsKIAkJY2xvY2tzb3VyY2VfY291bnRlci52ZHNv X2Nsb2NrX21vZGUgPSB2ZHNvX2RlZmF1bHQ7CiAJfSBlbHNlIHsKIAkJYXJjaF90aW1lcl9yZWFk X2NvdW50ZXIgPSBhcmNoX2NvdW50ZXJfZ2V0X2NudHZjdF9tZW07CgotLSAKV2l0aG91dCBkZXZp YXRpb24gZnJvbSB0aGUgbm9ybSwgcHJvZ3Jlc3MgaXMgbm90IHBvc3NpYmxlLgoKX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBt YWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9s aXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=