From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 462D779CD for ; Fri, 28 Nov 2025 15:51:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764345095; cv=none; b=LhsTFFYB0Bk8/KwmZ1kLVLBbsRYaRJ28WyWdQeBwhcT8M7xPJIVSprgdmyMxy8z0nnyLJhND+zx1i5J1Ph6Ugi1Cs7arjjhByTyNpSNgcStRHXYDGNnRFSYZO0pp9Jd4YRuhRJisFLK4Ew3ah9F58MoBSoZd7CM/rI73LOLRkK0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764345095; c=relaxed/simple; bh=aPLWofWdUipzpbGuIHYeHU8jUS57cqxPSIx0x6D8pto=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=LX7sW1Yh1JRR9qqtIMZt4M1+WgUEYnqmwIessJT87KyKqb0cJbdV457Zr9IG8GowMVtyyh6Vh4e805Pia6xg6jrRa+D/7wJZ8nkbhwf79xcv3QOfnj19J60kyo5L5O2y9/UbFgQ2+ceo4vR9jQLJkH3H5FA1CdY+vWJulH6Ywtg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lYmg2uDV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lYmg2uDV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BE878C4CEFB; Fri, 28 Nov 2025 15:51:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764345094; bh=aPLWofWdUipzpbGuIHYeHU8jUS57cqxPSIx0x6D8pto=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lYmg2uDVWyfjQSNLny1cLjM1VW7jsnTpJ4jPu+JkwIaBc0BqsEwCra07d+yDa9v0J ABgBqh9qO3MMC5amZ0IGnPsk53/ZRNufHBBRbEfnLGmLJ0EiFEBZ3A5PHE1ec8X8h8 7LEP0i1LUcOuyexzzFHUN8twOyh4lZPu67NsVgk63RTJhNfEA5ZtsgQ9IDgNp/MoqH Ce/CmifNmBO4F9I5P5e5LCNvDi90VMJQ1+smgMGQk/BVwg3Sgky+Hwgad7D7KRTh67 JkruvyNhp+xPhcRqH83Mk912YARDPRtHFgD+eh8uPFt0ILV4W9FccZn0Ggwb/XaPY/ YIuxUsTvuMBOQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vP0ku-000000097sK-1bwp; Fri, 28 Nov 2025 15:51:32 +0000 Date: Fri, 28 Nov 2025 15:51:31 +0000 Message-ID: <86tsyep33w.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: oliver.upton@linux.dev, joey.gouly@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: Re: [PATCH 4/4] KVM: arm64: at: Update AF on software walk only if VM has FEAT_HAFDBS In-Reply-To: <20251128100946.74210-5-alexandru.elisei@arm.com> References: <20251128100946.74210-1-alexandru.elisei@arm.com> <20251128100946.74210-5-alexandru.elisei@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, oliver.upton@linux.dev, joey.gouly@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 28 Nov 2025 10:09:46 +0000, Alexandru Elisei wrote: > > A guest can write 1 to TCR_ELx.HA, making the KVM software walker update > the access flag in a table descriptor even if FEAT_HAFDBS is not present. > Avoid this by making wi->ha depend on FEAT_HAFDBS being enabled in the VM, > similar to how the software walker treats FEAT_HPDS. > > This is not needed for VTCR_EL2.HA, since a guest will always write to > the in-memory copy of the register, where the HA bit is masked (set to > 0) by KVM if the VM doesn't have FEAT_HAFDBS. > > Fixes: c59ca4b5b0c3 ("KVM: arm64: Implement HW access flag management in stage-1 SW PTW") > Signed-off-by: Alexandru Elisei > --- > arch/arm64/kvm/at.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c > index 6d41a95f6c60..53bf70126f81 100644 > --- a/arch/arm64/kvm/at.c > +++ b/arch/arm64/kvm/at.c > @@ -346,7 +346,8 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, > > wi->baddr &= GENMASK_ULL(wi->max_oa_bits - 1, x); > > - wi->ha = (wi->regime == TR_EL2 ? > + wi->ha = kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, HAFDBS, AF); > + wi->ha &= (wi->regime == TR_EL2 ? > FIELD_GET(TCR_EL2_HA, tcr) : > FIELD_GET(TCR_HA, tcr)); This is yet another case where we should expand the sanitisation infrastructure to cover the TCR registers. Thanks, M. -- Without deviation from the norm, progress is not possible.