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<86ttwwh24b.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Atish Patra , Alistair Francis , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 5/9] irqchip: Add RISC-V incoming MSI controller driver In-Reply-To: References: <20230103141409.772298-1-apatel@ventanamicro.com> <20230103141409.772298-6-apatel@ventanamicro.com> <867cxqoic8.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230501_014503_696950_79C2A27F X-CRM114-Status: GOOD ( 57.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gTW9uLCAwMSBNYXkgMjAyMyAwOToyODoxNiArMDEwMCwKQW51cCBQYXRlbCA8YW51cEBicmFp bmZhdWx0Lm9yZz4gd3JvdGU6Cj4gCj4gT24gRnJpLCBKYW4gMTMsIDIwMjMgYXQgMzo0MOKAr1BN IE1hcmMgWnluZ2llciA8bWF6QGtlcm5lbC5vcmc+IHdyb3RlOgo+ID4KPiA+IE9uIFR1ZSwgMDMg SmFuIDIwMjMgMTQ6MTQ6MDUgKzAwMDAsCj4gPiBBbnVwIFBhdGVsIDxhcGF0ZWxAdmVudGFuYW1p Y3JvLmNvbT4gd3JvdGU6Cj4gPiA+Cj4gPiA+IFRoZSBSSVNDLVYgYWR2YW5jZWQgaW50ZXJydXB0 IGFyY2hpdGVjdHVyZSAoQUlBKSBzcGVjaWZpY2F0aW9uIGRlZmluZXMKPiA+ID4gYSBuZXcgTVNJ IGNvbnRyb2xsZXIgZm9yIG1hbmFnaW5nIE1TSXMgb24gYSBSSVNDLVYgcGxhdGZvcm0uIFRoaXMg bmV3Cj4gPiA+IE1TSSBjb250cm9sbGVyIGlzIHJlZmVycmVkIHRvIGFzIGluY29taW5nIG1lc3Nh Z2Ugc2lnbmFsZWQgaW50ZXJydXB0Cj4gPiA+IGNvbnRyb2xsZXIgKElNU0lDKSB3aGljaCBtYW5h Z2VzIE1TSSBvbiBwZXItSEFSVCAob3IgcGVyLUNQVSkgYmFzaXMuCj4gPiA+IChGb3IgbW9yZSBk ZXRhaWxzIHJlZmVyIGh0dHBzOi8vZ2l0aHViLmNvbS9yaXNjdi9yaXNjdi1haWEpCj4gPgo+ID4g QW5kIGhvdyBhYm91dCBJUElzLCB3aGljaCB0aGlzIGRyaXZlciBzZWVtcyB0byBiZSBjb25jZXJu ZWQgYWJvdXQ/Cj4gCj4gT2theSwgSSB3aWxsIG1lbnRpb24gYWJvdXQgSVBJcyBpbiB0aGUgY29t bWl0IGRlc2NyaXB0aW9uLgo+IAo+ID4KPiA+ID4KPiA+ID4gVGhpcyBwYXRjaCBhZGRzIGFuIGly cWNoaXAgZHJpdmVyIGZvciBSSVNDLVYgSU1TSUMgZm91bmQgb24gUklTQy1WCj4gPiA+IHBsYXRm b3Jtcy4KPiA+ID4KPiA+ID4gU2lnbmVkLW9mZi1ieTogQW51cCBQYXRlbCA8YXBhdGVsQHZlbnRh bmFtaWNyby5jb20+Cj4gPiA+IC0tLQo+ID4gPiAgZHJpdmVycy9pcnFjaGlwL0tjb25maWcgICAg ICAgICAgICAgfCAgIDE0ICstCj4gPiA+ICBkcml2ZXJzL2lycWNoaXAvTWFrZWZpbGUgICAgICAg ICAgICB8ICAgIDEgKwo+ID4gPiAgZHJpdmVycy9pcnFjaGlwL2lycS1yaXNjdi1pbXNpYy5jICAg fCAxMTc0ICsrKysrKysrKysrKysrKysrKysrKysrKysrKwo+ID4gPiAgaW5jbHVkZS9saW51eC9p cnFjaGlwL3Jpc2N2LWltc2ljLmggfCAgIDkyICsrKwo+ID4gPiAgNCBmaWxlcyBjaGFuZ2VkLCAx MjgwIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPiA+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0 NCBkcml2ZXJzL2lycWNoaXAvaXJxLXJpc2N2LWltc2ljLmMKPiA+ID4gIGNyZWF0ZSBtb2RlIDEw MDY0NCBpbmNsdWRlL2xpbnV4L2lycWNoaXAvcmlzY3YtaW1zaWMuaAo+ID4gPgo+ID4gPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9pcnFjaGlwL0tjb25maWcgYi9kcml2ZXJzL2lycWNoaXAvS2NvbmZp Zwo+ID4gPiBpbmRleCA5ZTY1MzQ1Y2EzZjYuLmExMzE1MTg5YTU5NSAxMDA2NDQKPiA+ID4gLS0t IGEvZHJpdmVycy9pcnFjaGlwL0tjb25maWcKPiA+ID4gKysrIGIvZHJpdmVycy9pcnFjaGlwL0tj b25maWcKPiA+ID4gQEAgLTI5LDcgKzI5LDYgQEAgY29uZmlnIEFSTV9HSUNfVjJNCj4gPiA+Cj4g PiA+ICBjb25maWcgR0lDX05PTl9CQU5LRUQKPiA+ID4gICAgICAgYm9vbAo+ID4gPiAtCj4gPiA+ ICBjb25maWcgQVJNX0dJQ19WMwo+ID4gPiAgICAgICBib29sCj4gPiA+ICAgICAgIHNlbGVjdCBJ UlFfRE9NQUlOX0hJRVJBUkNIWQo+ID4gPiBAQCAtNTQ4LDYgKzU0NywxOSBAQCBjb25maWcgU0lG SVZFX1BMSUMKPiA+ID4gICAgICAgc2VsZWN0IElSUV9ET01BSU5fSElFUkFSQ0hZCj4gPiA+ICAg ICAgIHNlbGVjdCBHRU5FUklDX0lSUV9FRkZFQ1RJVkVfQUZGX01BU0sgaWYgU01QCj4gPiA+Cj4g PiA+ICtjb25maWcgUklTQ1ZfSU1TSUMKPiA+ID4gKyAgICAgYm9vbAo+ID4gPiArICAgICBkZXBl bmRzIG9uIFJJU0NWCj4gPiA+ICsgICAgIHNlbGVjdCBJUlFfRE9NQUlOX0hJRVJBUkNIWQo+ID4g PiArICAgICBzZWxlY3QgR0VORVJJQ19NU0lfSVJRX0RPTUFJTgo+ID4gPiArCj4gPiA+ICtjb25m aWcgUklTQ1ZfSU1TSUNfUENJCj4gPiA+ICsgICAgIGJvb2wKPiA+ID4gKyAgICAgZGVwZW5kcyBv biBSSVNDVl9JTVNJQwo+ID4gPiArICAgICBkZXBlbmRzIG9uIFBDSQo+ID4gPiArICAgICBkZXBl bmRzIG9uIFBDSV9NU0kKPiA+ID4gKyAgICAgZGVmYXVsdCBSSVNDVl9JTVNJQwo+ID4KPiA+IFRo aXMgc2hvdWxkIGRlZmluaXRlbHkgdGVsbCB5b3UgdGhhdCB0aGlzIGRyaXZlciBuZWVkcyBzcGxp dHRpbmcuCj4gCj4gVGhlIGNvZGUgdW5kZXIgIiNpZmRlZiBDT05GSUdfUklTQ1ZfSU1TSUNfUENJ IiBpcyBoYXJkbHkgNDAgbGluZXMKPiBzbyBJIGZlbHQgaXQgd2FzIHRvbyBzbWFsbCB0byBkZXNl cnZlIGl0cyBvd24gc291cmNlIGZpbGUuCgpJdCBhdCBsZWFzdCBuZWVkcyBpdHMgb3duIHBhdGNo LgoKPiAKPiA+Cj4gPiA+ICsKPiA+ID4gIGNvbmZpZyBFWFlOT1NfSVJRX0NPTUJJTkVSCj4gPiA+ ICAgICAgIGJvb2wgIlNhbXN1bmcgRXh5bm9zIElSUSBjb21iaW5lciBzdXBwb3J0IiBpZiBDT01Q SUxFX1RFU1QKPiA+ID4gICAgICAgZGVwZW5kcyBvbiAoQVJDSF9FWFlOT1MgJiYgQVJNKSB8fCBD T01QSUxFX1RFU1QKPiA+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaXJxY2hpcC9NYWtlZmlsZSBi L2RyaXZlcnMvaXJxY2hpcC9NYWtlZmlsZQo+ID4gPiBpbmRleCA4N2I0OWExMDk2MmMuLjIyYzcy M2NjNmVjOCAxMDA2NDQKPiA+ID4gLS0tIGEvZHJpdmVycy9pcnFjaGlwL01ha2VmaWxlCj4gPiA+ ICsrKyBiL2RyaXZlcnMvaXJxY2hpcC9NYWtlZmlsZQo+ID4gPiBAQCAtOTYsNiArOTYsNyBAQCBv YmotJChDT05GSUdfUUNPTV9NUE0pICAgICAgICAgICAgICAgICAgICAgICs9IGlycS1xY29tLW1w bS5vCj4gPiA+ICBvYmotJChDT05GSUdfQ1NLWV9NUElOVEMpICAgICAgICAgICAgKz0gaXJxLWNz a3ktbXBpbnRjLm8KPiA+ID4gIG9iai0kKENPTkZJR19DU0tZX0FQQl9JTlRDKSAgICAgICAgICAr PSBpcnEtY3NreS1hcGItaW50Yy5vCj4gPiA+ICBvYmotJChDT05GSUdfUklTQ1ZfSU5UQykgICAg ICAgICAgICAgKz0gaXJxLXJpc2N2LWludGMubwo+ID4gPiArb2JqLSQoQ09ORklHX1JJU0NWX0lN U0lDKSAgICAgICAgICAgICs9IGlycS1yaXNjdi1pbXNpYy5vCj4gPiA+ICBvYmotJChDT05GSUdf U0lGSVZFX1BMSUMpICAgICAgICAgICAgKz0gaXJxLXNpZml2ZS1wbGljLm8KPiA+ID4gIG9iai0k KENPTkZJR19JTVhfSVJRU1RFRVIpICAgICAgICAgICArPSBpcnEtaW14LWlycXN0ZWVyLm8KPiA+ ID4gIG9iai0kKENPTkZJR19JTVhfSU5UTVVYKSAgICAgICAgICAgICArPSBpcnEtaW14LWludG11 eC5vCj4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2lycWNoaXAvaXJxLXJpc2N2LWltc2ljLmMg Yi9kcml2ZXJzL2lycWNoaXAvaXJxLXJpc2N2LWltc2ljLmMKPiA+ID4gbmV3IGZpbGUgbW9kZSAx MDA2NDQKPiA+ID4gaW5kZXggMDAwMDAwMDAwMDAwLi40YzE2YjY2NzM4ZDYKPiA+ID4gLS0tIC9k ZXYvbnVsbAo+ID4gPiArKysgYi9kcml2ZXJzL2lycWNoaXAvaXJxLXJpc2N2LWltc2ljLmMKPiA+ ID4gQEAgLTAsMCArMSwxMTc0IEBACj4gPiA+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjog R1BMLTIuMAo+ID4gPiArLyoKPiA+ID4gKyAqIENvcHlyaWdodCAoQykgMjAyMSBXZXN0ZXJuIERp Z2l0YWwgQ29ycG9yYXRpb24gb3IgaXRzIGFmZmlsaWF0ZXMuCj4gPiA+ICsgKiBDb3B5cmlnaHQg KEMpIDIwMjIgVmVudGFuYSBNaWNybyBTeXN0ZW1zIEluYy4KPiA+ID4gKyAqLwo+ID4gPiArCj4g PiA+ICsjZGVmaW5lIHByX2ZtdChmbXQpICJyaXNjdi1pbXNpYzogIiBmbXQKPiA+ID4gKyNpbmNs dWRlIDxsaW51eC9iaXRtYXAuaD4KPiA+ID4gKyNpbmNsdWRlIDxsaW51eC9jcHUuaD4KPiA+ID4g KyNpbmNsdWRlIDxsaW51eC9pbnRlcnJ1cHQuaD4KPiA+ID4gKyNpbmNsdWRlIDxsaW51eC9pby5o Pgo+ID4gPiArI2luY2x1ZGUgPGxpbnV4L2lvbW11Lmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgv aXJxLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvaXJxY2hpcC5oPgo+ID4gPiArI2luY2x1ZGUg PGxpbnV4L2lycWNoaXAvY2hhaW5lZF9pcnEuaD4KPiA+ID4gKyNpbmNsdWRlIDxsaW51eC9pcnFj aGlwL3Jpc2N2LWltc2ljLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvaXJxZG9tYWluLmg+Cj4g PiA+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvbXNp Lmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvb2YuaD4KPiA+ID4gKyNpbmNsdWRlIDxsaW51eC9v Zl9hZGRyZXNzLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvb2ZfaXJxLmg+Cj4gPiA+ICsjaW5j bHVkZSA8bGludXgvcGNpLmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNl Lmg+Cj4gPiA+ICsjaW5jbHVkZSA8bGludXgvc3BpbmxvY2suaD4KPiA+ID4gKyNpbmNsdWRlIDxs aW51eC9zbXAuaD4KPiA+ID4gKyNpbmNsdWRlIDxhc20vaHdjYXAuaD4KPiA+ID4gKwo+ID4gPiAr I2RlZmluZSBJTVNJQ19ESVNBQkxFX0VJREVMSVZFUlkgICAgIDAKPiA+ID4gKyNkZWZpbmUgSU1T SUNfRU5BQkxFX0VJREVMSVZFUlkgICAgICAgICAgICAgIDEKPiA+ID4gKyNkZWZpbmUgSU1TSUNf RElTQUJMRV9FSVRIUkVTSE9MRCAgICAxCj4gPiA+ICsjZGVmaW5lIElNU0lDX0VOQUJMRV9FSVRI UkVTSE9MRCAgICAgMAo+ID4gPiArCj4gPiA+ICsjZGVmaW5lIGltc2ljX2Nzcl93cml0ZShfX2Ms IF9fdikgICAgXAo+ID4gPiArZG8geyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwK PiA+ID4gKyAgICAgY3NyX3dyaXRlKENTUl9JU0VMRUNULCBfX2MpOyAgICBcCj4gPiA+ICsgICAg IGNzcl93cml0ZShDU1JfSVJFRywgX192KTsgICAgICAgXAo+ID4gPiArfSB3aGlsZSAoMCkKPiA+ ID4gKwo+ID4gPiArI2RlZmluZSBpbXNpY19jc3JfcmVhZChfX2MpICAgICAgICAgIFwKPiA+ID4g Kyh7ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiA+ICsgICAgIHVuc2ln bmVkIGxvbmcgX192OyAgICAgICAgICAgICAgXAo+ID4gPiArICAgICBjc3Jfd3JpdGUoQ1NSX0lT RUxFQ1QsIF9fYyk7ICAgIFwKPiA+ID4gKyAgICAgX192ID0gY3NyX3JlYWQoQ1NSX0lSRUcpOyAg ICAgICBcCj4gPiA+ICsgICAgIF9fdjsgICAgICAgICAgICAgICAgICAgICAgICAgICAgXAo+ID4g PiArfSkKPiA+ID4gKwo+ID4gPiArI2RlZmluZSBpbXNpY19jc3Jfc2V0KF9fYywgX192KSAgICAg ICAgICAgICAgXAo+ID4gPiArZG8geyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwK PiA+ID4gKyAgICAgY3NyX3dyaXRlKENTUl9JU0VMRUNULCBfX2MpOyAgICBcCj4gPiA+ICsgICAg IGNzcl9zZXQoQ1NSX0lSRUcsIF9fdik7ICAgICAgICAgXAo+ID4gPiArfSB3aGlsZSAoMCkKPiA+ ID4gKwo+ID4gPiArI2RlZmluZSBpbXNpY19jc3JfY2xlYXIoX19jLCBfX3YpICAgIFwKPiA+ID4g K2RvIHsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4gPiA+ICsgICAgIGNzcl93 cml0ZShDU1JfSVNFTEVDVCwgX19jKTsgICAgXAo+ID4gPiArICAgICBjc3JfY2xlYXIoQ1NSX0lS RUcsIF9fdik7ICAgICAgIFwKPiA+ID4gK30gd2hpbGUgKDApCj4gPiA+ICsKPiA+ID4gK3N0cnVj dCBpbXNpY19tbWlvIHsKPiA+ID4gKyAgICAgcGh5c19hZGRyX3QgcGE7Cj4gPiA+ICsgICAgIHZv aWQgX19pb21lbSAqdmE7Cj4gPiA+ICsgICAgIHVuc2lnbmVkIGxvbmcgc2l6ZTsKPiA+ID4gK307 Cj4gPiA+ICsKPiA+ID4gK3N0cnVjdCBpbXNpY19wcml2IHsKPiA+ID4gKyAgICAgLyogR2xvYmFs IGNvbmZpZ3VyYXRpb24gY29tbW9uIGZvciBhbGwgSEFSVHMgKi8KPiA+ID4gKyAgICAgc3RydWN0 IGltc2ljX2dsb2JhbF9jb25maWcgZ2xvYmFsOwo+ID4gPiArCj4gPiA+ICsgICAgIC8qIE1NSU8g cmVnaW9ucyAqLwo+ID4gPiArICAgICB1MzIgbnVtX21taW9zOwo+ID4gPiArICAgICBzdHJ1Y3Qg aW1zaWNfbW1pbyAqbW1pb3M7Cj4gPiA+ICsKPiA+ID4gKyAgICAgLyogR2xvYmFsIHN0YXRlIG9m IGludGVycnVwdCBpZGVudGl0aWVzICovCj4gPiA+ICsgICAgIHJhd19zcGlubG9ja190IGlkc19s b2NrOwo+ID4gPiArICAgICB1bnNpZ25lZCBsb25nICppZHNfdXNlZF9iaW1hcDsKPiA+ID4gKyAg ICAgdW5zaWduZWQgbG9uZyAqaWRzX2VuYWJsZWRfYmltYXA7Cj4gPiA+ICsgICAgIHVuc2lnbmVk IGludCAqaWRzX3RhcmdldF9jcHU7Cj4gPiA+ICsKPiA+ID4gKyAgICAgLyogTWFzayBmb3IgY29u bmVjdGVkIENQVXMgKi8KPiA+ID4gKyAgICAgc3RydWN0IGNwdW1hc2sgbG1hc2s7Cj4gPiA+ICsK PiA+ID4gKyAgICAgLyogSVBJIGludGVycnVwdCBpZGVudGl0eSAqLwo+ID4gPiArICAgICB1MzIg aXBpX2lkOwo+ID4gPiArICAgICB1MzIgaXBpX2xzeW5jX2lkOwo+ID4gPiArCj4gPiA+ICsgICAg IC8qIElSUSBkb21haW5zICovCj4gPiA+ICsgICAgIHN0cnVjdCBpcnFfZG9tYWluICpiYXNlX2Rv bWFpbjsKPiA+ID4gKyAgICAgc3RydWN0IGlycV9kb21haW4gKnBjaV9kb21haW47Cj4gPiA+ICsg ICAgIHN0cnVjdCBpcnFfZG9tYWluICpwbGF0X2RvbWFpbjsKPiA+ID4gK307Cj4gPiA+ICsKPiA+ ID4gK3N0cnVjdCBpbXNpY19oYW5kbGVyIHsKPiA+ID4gKyAgICAgLyogTG9jYWwgY29uZmlndXJh dGlvbiBmb3IgZ2l2ZW4gSEFSVCAqLwo+ID4gPiArICAgICBzdHJ1Y3QgaW1zaWNfbG9jYWxfY29u ZmlnIGxvY2FsOwo+ID4gPiArCj4gPiA+ICsgICAgIC8qIFBvaW50ZXIgdG8gcHJpdmF0ZSBjb250 ZXh0ICovCj4gPiA+ICsgICAgIHN0cnVjdCBpbXNpY19wcml2ICpwcml2Owo+ID4gPiArfTsKPiA+ ID4gKwo+ID4gPiArc3RhdGljIGJvb2wgaW1zaWNfaW5pdF9kb25lOwo+ID4gPiArCj4gPiA+ICtz dGF0aWMgaW50IGltc2ljX3BhcmVudF9pcnE7Cj4gPiA+ICtzdGF0aWMgREVGSU5FX1BFUl9DUFUo c3RydWN0IGltc2ljX2hhbmRsZXIsIGltc2ljX2hhbmRsZXJzKTsKPiA+ID4gKwo+ID4gPiArY29u c3Qgc3RydWN0IGltc2ljX2dsb2JhbF9jb25maWcgKmltc2ljX2dldF9nbG9iYWxfY29uZmlnKHZv aWQpCj4gPiA+ICt7Cj4gPiA+ICsgICAgIHN0cnVjdCBpbXNpY19oYW5kbGVyICpoYW5kbGVyID0g dGhpc19jcHVfcHRyKCZpbXNpY19oYW5kbGVycyk7Cj4gPiA+ICsKPiA+ID4gKyAgICAgaWYgKCFo YW5kbGVyIHx8ICFoYW5kbGVyLT5wcml2KQo+ID4gPiArICAgICAgICAgICAgIHJldHVybiBOVUxM Owo+ID4gPiArCj4gPiA+ICsgICAgIHJldHVybiAmaGFuZGxlci0+cHJpdi0+Z2xvYmFsOwo+ID4g PiArfQo+ID4gPiArRVhQT1JUX1NZTUJPTF9HUEwoaW1zaWNfZ2V0X2dsb2JhbF9jb25maWcpOwo+ ID4gPiArCj4gPiA+ICtjb25zdCBzdHJ1Y3QgaW1zaWNfbG9jYWxfY29uZmlnICppbXNpY19nZXRf bG9jYWxfY29uZmlnKHVuc2lnbmVkIGludCBjcHUpCj4gPiA+ICt7Cj4gPiA+ICsgICAgIHN0cnVj dCBpbXNpY19oYW5kbGVyICpoYW5kbGVyID0gcGVyX2NwdV9wdHIoJmltc2ljX2hhbmRsZXJzLCBj cHUpOwo+ID4gPiArCj4gPiA+ICsgICAgIGlmICghaGFuZGxlciB8fCAhaGFuZGxlci0+cHJpdikK PiA+ID4gKyAgICAgICAgICAgICByZXR1cm4gTlVMTDsKPiA+Cj4gPiBIb3cgY2FuIHRoaXMgaGFw cGVuPwo+IAo+IFRoZXNlIGFyZSByZWR1bmRhbnQgY2hlY2tzLiBJIHdpbGwgZHJvcC4KPiAKPiA+ Cj4gPiA+ICsKPiA+ID4gKyAgICAgcmV0dXJuICZoYW5kbGVyLT5sb2NhbDsKPiA+ID4gK30KPiA+ ID4gK0VYUE9SVF9TWU1CT0xfR1BMKGltc2ljX2dldF9sb2NhbF9jb25maWcpOwo+ID4KPiA+IFdo eSBhcmUgdGhlc2Ugc3ltYm9scyBleHBvcnRlZD8gVGhleSBoYXZlIG5vIHVzZXIsIHNvIHRoZXkg c2hvdWxkbid0Cj4gPiBldmVuIGV4aXN0IGhlcmUuIEkgYWxzbyBzZXJpb3VzbHkgZG91YnQgdGhl cmUgaXMgYSB2YWxpZCB1c2UgY2FzZSBmb3IKPiA+IGV4cG9zaW5nIHRoaXMgaW5mb3JtYXRpb24g dG8gdGhlIHJlc3Qgb2YgdGhlIGtlcm5lbC4KPiAKPiBUaGUgaW1zaWNfZ2V0X2dsb2JhbF9jb25m aWcoKSBpcyB1c2VkIGJ5IEFQTElDIGRyaXZlciBhbmQgS1ZNIFJJU0MtVgo+IG1vZHVsZSB3aGVy ZWFzIGltc2ljX2dldF9sb2NhbF9jb25maWcoKSBpcyBvbmx5IHVzZWQgYnkgS1ZNIFJJU0MtVi4K PiAKPiBUaGUgS1ZNIFJJU0MtViBBSUEgaXJxY2hpcCBwYXRjaGVzIGFyZSBhdmFpbGFibGUgaW4g cmlzY3Zfa3ZtX2FpYV92MQo+IGJyYW5jaCBhdDogaHR0cHM6Ly9naXRodWIuY29tL2F2cGF0ZWwv bGludXguZ2l0LiBJIGhhdmUgbm90IHBvc3RlZCBLVk0gUklTQy1WCj4gcGF0Y2hlcyBkdWUgdmFy aW91cyBpbnRlcmRlcGVuZGVuY2llcy4KClRoZW4gdGhlIHN5bWJvbHMgY2FuIHdhaXQsIGNhbid0 IHRoZXk/IEl0J2QgbWFrZSBtb3JlIHNlbnNlIGlmIHRoZQpLVk0tZGVwZW5kZW50IGJpdHMgd2Vy ZSBicm91Z2h0IHRvZ2V0aGVyIHdpdGggdGhlIEtWTSBwYXRjaGVzLgoKRXZlbiBiZXR0ZXIsIHlv dSdkIHVzZSBzb21lIGxldmVsIG9mIGFic3RyYWN0aW9uIGJldHdlZW4gS1ZNIGFuZCB0aGUKaXJx Y2hpcCBjb2RlLiBHSUMgbWFrZXMgc29tZSBoZWF2eSB1c2Ugb2YgaXJxX3NldF92Y3B1X2FmZmlu aXR5KCkgYXMgYQpwcml2YXRlIEFQSSB3aXRoIEtWTSwgYW5kIEknZCBzdWdnZXN0IHlvdSBsb29r IGludG8gc29tZXRoaW5nIHNpbWlsYXIuCgpbLi4uXQoKPiA+ID4gKyNpZmRlZiBDT05GSUdfU01Q Cj4gPiA+ICtzdGF0aWMgdm9pZCBfX2ltc2ljX2lkX3NtcF9zeW5jKHN0cnVjdCBpbXNpY19wcml2 ICpwcml2KQo+ID4gPiArewo+ID4gPiArICAgICBzdHJ1Y3QgaW1zaWNfaGFuZGxlciAqaGFuZGxl cjsKPiA+ID4gKyAgICAgc3RydWN0IGNwdW1hc2sgYW1hc2s7Cj4gPiA+ICsgICAgIGludCBjcHU7 Cj4gPiA+ICsKPiA+ID4gKyAgICAgY3B1bWFza19hbmQoJmFtYXNrLCAmcHJpdi0+bG1hc2ssIGNw dV9vbmxpbmVfbWFzayk7Cj4gPgo+ID4gQ2FuJ3QgdGhpcyByYWNlIGFnYWluc3QgYSBDUFUgZ29p bmcgZG93bj8KPiAKPiBZZXMsIGl0IGNhbiByYWNlIGlmIGEgQ1BVIGdvZXMgZG93biB3aGlsZSB3 ZSBhcmUgaW4gdGhpcyBmdW5jdGlvbgo+IGJ1dCB0aGlzIHdvbid0IGJlIGEgcHJvYmxlbSBiZWNh dXNlIHRoZSBpbXNpY19zdGFydGluZ19jcHUoKQo+IHdpbGwgdW5jb25kaXRpb25hbGx5IGRvIGlt c2ljX2lkc19sb2NhbF9zeW5jKCkgd2hlbiB0aGUgQ1BVIGlzCj4gYnJvdWdodC11cCBhZ2Fpbi4g SSB3aWxsIGFkZCBhIG11bHRpbGluZSBjb21tZW50IGJsb2NrIGV4cGxhaW5pbmcKPiB0aGlzLgoK SSdkIHJhdGhlciB5b3UgYXZvaWQgdGhlIHJhY2UgaW5zdGVhZCBvZiBwYXBlcmluZyBvdmVyIGl0 LgoKPiAKPiA+Cj4gPiA+ICsgICAgIGZvcl9lYWNoX2NwdShjcHUsICZhbWFzaykgewo+ID4gPiAr ICAgICAgICAgICAgIGlmIChjcHUgPT0gc21wX3Byb2Nlc3Nvcl9pZCgpKQo+ID4gPiArICAgICAg ICAgICAgICAgICAgICAgY29udGludWU7Cj4gPiA+ICsKPiA+ID4gKyAgICAgICAgICAgICBoYW5k bGVyID0gcGVyX2NwdV9wdHIoJmltc2ljX2hhbmRsZXJzLCBjcHUpOwo+ID4gPiArICAgICAgICAg ICAgIGlmICghaGFuZGxlciB8fCAhaGFuZGxlci0+cHJpdiB8fCAhaGFuZGxlci0+bG9jYWwubXNp X3ZhKSB7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICBwcl93YXJuKCJDUFUlZDogaGFuZGxl ciBub3QgaW5pdGlhbGl6ZWRcbiIsIGNwdSk7Cj4gPgo+ID4gSG93IG1hbnkgdGltZXMgYXJlIHlv dSBnb2luZyB0byBkbyB0aGF0PyBPbiBlYWNoIGZhaWxpbmcgc3luY2hyb25pc2F0aW9uPwo+IAo+ IE15IGJhZCBmb3IgYWRkaW5nIHRoZXNlIHBhcmFub2lkIGNoZWNrcy4gSSByZW1vdmUgdGhlc2Ug Y2hlY2tzCj4gd2hlcmV2ZXIgcG9zc2libGUuCj4gCj4gPgo+ID4gPiArICAgICAgICAgICAgICAg ICAgICAgY29udGludWU7Cj4gPiA+ICsgICAgICAgICAgICAgfQo+ID4gPiArCj4gPiA+ICsgICAg ICAgICAgICAgd3JpdGVsKGhhbmRsZXItPnByaXYtPmlwaV9sc3luY19pZCwgaGFuZGxlci0+bG9j YWwubXNpX3ZhKTsKPiA+Cj4gPiBBcyBJIHVuZGVyc3RhbmQgaXQsIHRoaXMgaXMgYSAiYmVoaW5k IHRoZSBzY2VuZXMiIElQSS4gV2h5IGlzbid0IHRoYXQKPiA+IGEgKnJlYWwqIElQST8KPiAKPiBZ ZXMsIHRoYXQncyBjb3JyZWN0LiBUaGUgSUQgZW5hYmxlIGJpdHMgYXJlIHBlci1DUFUgYWNjZXNz aWJsZSBvbmx5Cj4gdmlhIENTUnMgaGVuY2Ugd2UgaGF2ZSBhIHNwZWNpYWwgImJlaGluZCB0aGUg c2NlbmVzIiBJUEkgdG8KPiBzeW5jaHJvbml6ZSBzdGF0ZSBvZiBJRCBlbmFibGUgYml0cy4KCk15 IHF1ZXN0aW9uIHN0aWxsIHN0YW5kczogd2h5IGlzbid0IHRoaXMgYSAqcmVhbCosIExpbnV4IHZp c2libGUgSVBJPwpUaGlzIHNpZGViYW5kIHNpZ25hbGxpbmcgbWFrZXMgZXZlcnl0aGluZyBoYXJk IHRvIGZvbGxvdywgaGFyZCB0bwpkZWJ1ZywgYW5kIHNjcmV3cyB1cCBhY2NvdW50aW5nLgoKPiA+ IFBsZWFzZSBzcGxpdCB0aGUgd2hvbGUgZ3Vlc3Qgc3R1ZmYgb3V0LiBJdCBpcyB0b3RhbGx5IHVu dXNlZCEKPiAKPiBUaGUgbnVtYmVyIG9mIGd1ZXN0IElEcyBpcyB1c2VkIGJ5IEtWTSBSSVNDLVYg QUlBIHN1cHBvcnQgd2hpY2gKPiBpcyBpbiB0aGUgcGlwZWxpbmUuIFRoZSBLVk0gUklTQy1WIG9u bHkgbmVlZCBpbXNpY19nZXRfZ2xvYmFsX2NvbmZpZygpCj4gYW5kIGltc2ljX2dldF9sb2NhbF9j b25maWcoKS4gVGhlICJucl9ndWVzdF9pZHMiIGlzIHBhcnQgb2YgdGhlCj4gSU1TSUMgZ2xvYmFs IGNvbmZpZy4KCkFuZCB5ZXQgaXQgaXNuJ3QgbmVlZGVkIGZvciBhIG1pbmltYWwgZHJpdmVyLCB3 aGljaCB3aGF0IEknZCBsaWtlIHRvCnNlZSBhdCBmaXJzdC4gU2hvdmluZyB0aGUga2l0Y2hlbiBz aW5rIGludG8gYW4gaW5pdGlhbCBwYXRjaCBpc24ndCBhCmdyZWF0IHdheSB0byBnZXQgaXQgbWVy Z2VkLgoKICAgICAgTS4KCi0tIApXaXRob3V0IGRldmlhdGlvbiBmcm9tIHRoZSBub3JtLCBwcm9n cmVzcyBpcyBub3QgcG9zc2libGUuCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpsaW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMu aW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZv 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(envelope-from ) id 1ptP9V-00CFJx-9A; Mon, 01 May 2023 09:44:57 +0100 Date: Mon, 01 May 2023 09:44:52 +0100 Message-ID: <86ttwwh24b.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Atish Patra , Alistair Francis , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 5/9] irqchip: Add RISC-V incoming MSI controller driver In-Reply-To: References: <20230103141409.772298-1-apatel@ventanamicro.com> <20230103141409.772298-6-apatel@ventanamicro.com> <867cxqoic8.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anup@brainfault.org, apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, 01 May 2023 09:28:16 +0100, Anup Patel wrote: >=20 > On Fri, Jan 13, 2023 at 3:40=E2=80=AFPM Marc Zyngier wro= te: > > > > On Tue, 03 Jan 2023 14:14:05 +0000, > > Anup Patel wrote: > > > > > > The RISC-V advanced interrupt architecture (AIA) specification defines > > > a new MSI controller for managing MSIs on a RISC-V platform. This new > > > MSI controller is referred to as incoming message signaled interrupt > > > controller (IMSIC) which manages MSI on per-HART (or per-CPU) basis. > > > (For more details refer https://github.com/riscv/riscv-aia) > > > > And how about IPIs, which this driver seems to be concerned about? >=20 > Okay, I will mention about IPIs in the commit description. >=20 > > > > > > > > This patch adds an irqchip driver for RISC-V IMSIC found on RISC-V > > > platforms. > > > > > > Signed-off-by: Anup Patel > > > --- > > > drivers/irqchip/Kconfig | 14 +- > > > drivers/irqchip/Makefile | 1 + > > > drivers/irqchip/irq-riscv-imsic.c | 1174 +++++++++++++++++++++++++= ++ > > > include/linux/irqchip/riscv-imsic.h | 92 +++ > > > 4 files changed, 1280 insertions(+), 1 deletion(-) > > > create mode 100644 drivers/irqchip/irq-riscv-imsic.c > > > create mode 100644 include/linux/irqchip/riscv-imsic.h > > > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > > index 9e65345ca3f6..a1315189a595 100644 > > > --- a/drivers/irqchip/Kconfig > > > +++ b/drivers/irqchip/Kconfig > > > @@ -29,7 +29,6 @@ config ARM_GIC_V2M > > > > > > config GIC_NON_BANKED > > > bool > > > - > > > config ARM_GIC_V3 > > > bool > > > select IRQ_DOMAIN_HIERARCHY > > > @@ -548,6 +547,19 @@ config SIFIVE_PLIC > > > select IRQ_DOMAIN_HIERARCHY > > > select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP > > > > > > +config RISCV_IMSIC > > > + bool > > > + depends on RISCV > > > + select IRQ_DOMAIN_HIERARCHY > > > + select GENERIC_MSI_IRQ_DOMAIN > > > + > > > +config RISCV_IMSIC_PCI > > > + bool > > > + depends on RISCV_IMSIC > > > + depends on PCI > > > + depends on PCI_MSI > > > + default RISCV_IMSIC > > > > This should definitely tell you that this driver needs splitting. >=20 > The code under "#ifdef CONFIG_RISCV_IMSIC_PCI" is hardly 40 lines > so I felt it was too small to deserve its own source file. It at least needs its own patch. >=20 > > > > > + > > > config EXYNOS_IRQ_COMBINER > > > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > > > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > > > index 87b49a10962c..22c723cc6ec8 100644 > > > --- a/drivers/irqchip/Makefile > > > +++ b/drivers/irqchip/Makefile > > > @@ -96,6 +96,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D ir= q-qcom-mpm.o > > > obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o > > > obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o > > > obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o > > > +obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic.o > > > obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o > > > obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o > > > obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o > > > diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-= riscv-imsic.c > > > new file mode 100644 > > > index 000000000000..4c16b66738d6 > > > --- /dev/null > > > +++ b/drivers/irqchip/irq-riscv-imsic.c > > > @@ -0,0 +1,1174 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Copyright (C) 2021 Western Digital Corporation or its affiliates. > > > + * Copyright (C) 2022 Ventana Micro Systems Inc. > > > + */ > > > + > > > +#define pr_fmt(fmt) "riscv-imsic: " fmt > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#define IMSIC_DISABLE_EIDELIVERY 0 > > > +#define IMSIC_ENABLE_EIDELIVERY 1 > > > +#define IMSIC_DISABLE_EITHRESHOLD 1 > > > +#define IMSIC_ENABLE_EITHRESHOLD 0 > > > + > > > +#define imsic_csr_write(__c, __v) \ > > > +do { \ > > > + csr_write(CSR_ISELECT, __c); \ > > > + csr_write(CSR_IREG, __v); \ > > > +} while (0) > > > + > > > +#define imsic_csr_read(__c) \ > > > +({ \ > > > + unsigned long __v; \ > > > + csr_write(CSR_ISELECT, __c); \ > > > + __v =3D csr_read(CSR_IREG); \ > > > + __v; \ > > > +}) > > > + > > > +#define imsic_csr_set(__c, __v) \ > > > +do { \ > > > + csr_write(CSR_ISELECT, __c); \ > > > + csr_set(CSR_IREG, __v); \ > > > +} while (0) > > > + > > > +#define imsic_csr_clear(__c, __v) \ > > > +do { \ > > > + csr_write(CSR_ISELECT, __c); \ > > > + csr_clear(CSR_IREG, __v); \ > > > +} while (0) > > > + > > > +struct imsic_mmio { > > > + phys_addr_t pa; > > > + void __iomem *va; > > > + unsigned long size; > > > +}; > > > + > > > +struct imsic_priv { > > > + /* Global configuration common for all HARTs */ > > > + struct imsic_global_config global; > > > + > > > + /* MMIO regions */ > > > + u32 num_mmios; > > > + struct imsic_mmio *mmios; > > > + > > > + /* Global state of interrupt identities */ > > > + raw_spinlock_t ids_lock; > > > + unsigned long *ids_used_bimap; > > > + unsigned long *ids_enabled_bimap; > > > + unsigned int *ids_target_cpu; > > > + > > > + /* Mask for connected CPUs */ > > > + struct cpumask lmask; > > > + > > > + /* IPI interrupt identity */ > > > + u32 ipi_id; > > > + u32 ipi_lsync_id; > > > + > > > + /* IRQ domains */ > > > + struct irq_domain *base_domain; > > > + struct irq_domain *pci_domain; > > > + struct irq_domain *plat_domain; > > > +}; > > > + > > > +struct imsic_handler { > > > + /* Local configuration for given HART */ > > > + struct imsic_local_config local; > > > + > > > + /* Pointer to private context */ > > > + struct imsic_priv *priv; > > > +}; > > > + > > > +static bool imsic_init_done; > > > + > > > +static int imsic_parent_irq; > > > +static DEFINE_PER_CPU(struct imsic_handler, imsic_handlers); > > > + > > > +const struct imsic_global_config *imsic_get_global_config(void) > > > +{ > > > + struct imsic_handler *handler =3D this_cpu_ptr(&imsic_handlers); > > > + > > > + if (!handler || !handler->priv) > > > + return NULL; > > > + > > > + return &handler->priv->global; > > > +} > > > +EXPORT_SYMBOL_GPL(imsic_get_global_config); > > > + > > > +const struct imsic_local_config *imsic_get_local_config(unsigned int= cpu) > > > +{ > > > + struct imsic_handler *handler =3D per_cpu_ptr(&imsic_handlers, = cpu); > > > + > > > + if (!handler || !handler->priv) > > > + return NULL; > > > > How can this happen? >=20 > These are redundant checks. I will drop. >=20 > > > > > + > > > + return &handler->local; > > > +} > > > +EXPORT_SYMBOL_GPL(imsic_get_local_config); > > > > Why are these symbols exported? They have no user, so they shouldn't > > even exist here. I also seriously doubt there is a valid use case for > > exposing this information to the rest of the kernel. >=20 > The imsic_get_global_config() is used by APLIC driver and KVM RISC-V > module whereas imsic_get_local_config() is only used by KVM RISC-V. >=20 > The KVM RISC-V AIA irqchip patches are available in riscv_kvm_aia_v1 > branch at: https://github.com/avpatel/linux.git. I have not posted KVM RI= SC-V > patches due various interdependencies. Then the symbols can wait, can't they? It'd make more sense if the KVM-dependent bits were brought together with the KVM patches. Even better, you'd use some level of abstraction between KVM and the irqchip code. GIC makes some heavy use of irq_set_vcpu_affinity() as a private API with KVM, and I'd suggest you look into something similar. [...] > > > +#ifdef CONFIG_SMP > > > +static void __imsic_id_smp_sync(struct imsic_priv *priv) > > > +{ > > > + struct imsic_handler *handler; > > > + struct cpumask amask; > > > + int cpu; > > > + > > > + cpumask_and(&amask, &priv->lmask, cpu_online_mask); > > > > Can't this race against a CPU going down? >=20 > Yes, it can race if a CPU goes down while we are in this function > but this won't be a problem because the imsic_starting_cpu() > will unconditionally do imsic_ids_local_sync() when the CPU is > brought-up again. I will add a multiline comment block explaining > this. I'd rather you avoid the race instead of papering over it. >=20 > > > > > + for_each_cpu(cpu, &amask) { > > > + if (cpu =3D=3D smp_processor_id()) > > > + continue; > > > + > > > + handler =3D per_cpu_ptr(&imsic_handlers, cpu); > > > + if (!handler || !handler->priv || !handler->local.msi_v= a) { > > > + pr_warn("CPU%d: handler not initialized\n", cpu= ); > > > > How many times are you going to do that? On each failing synchronisatio= n? >=20 > My bad for adding these paranoid checks. I remove these checks > wherever possible. >=20 > > > > > + continue; > > > + } > > > + > > > + writel(handler->priv->ipi_lsync_id, handler->local.msi_= va); > > > > As I understand it, this is a "behind the scenes" IPI. Why isn't that > > a *real* IPI? >=20 > Yes, that's correct. The ID enable bits are per-CPU accessible only > via CSRs hence we have a special "behind the scenes" IPI to > synchronize state of ID enable bits. My question still stands: why isn't this a *real*, Linux visible IPI? This sideband signalling makes everything hard to follow, hard to debug, and screws up accounting. > > Please split the whole guest stuff out. It is totally unused! >=20 > The number of guest IDs is used by KVM RISC-V AIA support which > is in the pipeline. The KVM RISC-V only need imsic_get_global_config() > and imsic_get_local_config(). The "nr_guest_ids" is part of the > IMSIC global config. And yet it isn't needed for a minimal driver, which what I'd like to see at first. Shoving the kitchen sink into an initial patch isn't a great way to get it merged. M. --=20 Without deviation from the norm, progress is not possible.