From: Marc Zyngier <maz@kernel.org>
To: salil.mehta@opnsrc.net
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, salil.mehta@huawei.com,
jonathan.cameron@huawei.com, will@kernel.org,
catalin.marinas@arm.com, mark.rutland@arm.com,
james.morse@arm.com, sudeep.holla@arm.com, lpieralisi@kernel.org,
jean-philippe@linaro.org, tglx@linutronix.de,
oliver.upton@linux.dev, peter.maydell@linaro.org,
richard.henderson@linaro.org, andrew.jones@linux.dev,
mst@redhat.com, david@redhat.com, philmd@linaro.org,
ardb@kernel.org, borntraeger@linux.ibm.com,
alex.bennee@linaro.org, gustavo.romero@linaro.org,
npiggin@gmail.com, linux@armlinux.org.uk,
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gankulkarni@os.amperecomputing.com, wangyanan55@huawei.com,
wangzhou1@hisilicon.com, linuxarm@huawei.com
Subject: Re: [RFC PATCH] KVM: arm64: vgic-v3: Cache ICC_CTLR_EL1 and allow lockless read when ready
Date: Thu, 09 Oct 2025 14:48:40 +0100 [thread overview]
Message-ID: <86v7koxk1z.wl-maz@kernel.org> (raw)
In-Reply-To: <20251008201955.3919537-1-salil.mehta@opnsrc.net>
On Wed, 08 Oct 2025 21:19:55 +0100,
salil.mehta@opnsrc.net wrote:
>
> From: Salil Mehta <salil.mehta@huawei.com>
>
> [A rough illustration of the problem and the probable solution]
>
> Userspace reads of ICC_CTLR_EL1 via KVM device attributes currently takes a slow
> path that may acquire all vCPU locks. Under workloads that exercise userspace
> PSCI CPU_ON flows or frequent vCPU resets, this can cause vCPU lock contention
> in KVM and, in the worst cases, -EBUSY returns to userspace.
>
> When PSCI CPU_ON and CPU_OFF calls are handled entirely in KVM, these operations
> are executed under KVM vCPU locks in the host kernel (EL1) and appear atomic to
> other vCPU threads. In this context, system register accesses are serialized
> under KVM vCPU locks, ensuring atomicity with respect to other vCPUs. After
> SMCCC filtering was introduced, PSCI CPU_ON and CPU_OFF calls can now exit to
> userspace (QEMU). During the handling of PSCI CPU_ON call in userspace, a
> cpu_reset() is exerted which reads ICC_CTLR_EL1 through KVM device attribute
> IOCTLs. To avoid transient inconsistency and -EBUSY errors, QEMU is forced to
> pause all vCPUs before issuing these IOCTLs.
I'm going to repeat in public what I already said in private.
Why does QEMU need to know this? I don't see how this is related to
PSCI, and outside of save/restore, there is no reason why QEMU should
poke at this. If QEMU needs fixing, please fix QEMU.
Honestly, I don't see why the kernel should even care about this, and
I have no intention of adopting anything of the sort for something
that has all the hallmarks of a userspace bug.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-10-09 13:49 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 20:19 [RFC PATCH] KVM: arm64: vgic-v3: Cache ICC_CTLR_EL1 and allow lockless read when ready salil.mehta
2025-10-09 13:48 ` Marc Zyngier [this message]
2025-10-13 8:42 ` Peter Maydell
2025-10-13 10:54 ` Marc Zyngier
2025-10-13 16:48 ` Peter Maydell
2025-10-14 3:02 ` Salil Mehta
2025-10-14 9:31 ` Peter Maydell
2025-10-14 9:50 ` Salil Mehta
2025-10-14 7:44 ` Marc Zyngier
2025-10-14 9:33 ` Peter Maydell
2025-10-14 10:24 ` Salil Mehta
2025-10-13 15:48 ` Salil Mehta
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