From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 939081A4E70 for ; Thu, 19 Dec 2024 18:16:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734632166; cv=none; b=dWzK+x2bH9et6Iu7F01vC4VqSDWz67Gc1nvNk6fnAalu/8S/kYZeh1WZzcDESqlRNq4zRqF5IfpNR+s52HH+Bli6yAex4vR5V8QpkFUYyhJc+Bje/qvJjH5eMU+U63jVeAZMnRtO+RcjZprxKokoq0MzI0xxOitKJ04U9ZruNGI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734632166; c=relaxed/simple; bh=6Ru1WifqyFOFkxxpz2vHqG7YF2grfX7gaaKnKpi5JK4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=GWQqL2nDsGDm2Q1Tqmd6RMeYAISqG1SvNLJ4IEkzn5U5hxsitcsXcaKE6qJWpgYALEvUZ3Sa2U2eVNuSDSd9wNNFsQAbFtkKr7ksZMAbeGapJdimtG7fLR/UGQRdiewzSJfD6cPE7r1K8vX764PCNORRyoOjupfALkvVRff+r8Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CVf0+wfY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CVf0+wfY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32E71C4CED6; Thu, 19 Dec 2024 18:16:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734632166; bh=6Ru1WifqyFOFkxxpz2vHqG7YF2grfX7gaaKnKpi5JK4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=CVf0+wfYKxa/renOq5MaNRGIh7QLPi2sGQz4XdDVlx6lwi3LuugU1Oepktp00Trmf ThvtxPjbyji+HcfO7LSPXyCULXFmt+PDis8LIzmDkam78XLoCkEsP+ozxbXLAh26+A KXm0eqUtWvvwUiszPMRSlFrcOH2iprGb89/UzJHCjaA6cTPmx6L1tM8rk5Qo/TKDDl wcvXH9TpExcKY7/6dydHALmrFzkoPPnv8ZirNsStAqKuBeBymjb8jZobR/+jsUmwhr CAY6usaGgZ/5xaqrTbPCPDtpNfWVG2ku2M5Yam5lZGBBoPinW7R13fwMvQrHj/YVZK sf1JgzdS7U4pg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tOL46-005McR-SJ; Thu, 19 Dec 2024 18:16:03 +0000 Date: Thu, 19 Dec 2024 18:16:02 +0000 Message-ID: <86wmfvpmhp.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , James Clark Subject: Re: [PATCH v3 12/16] KVM: arm64: Compute MDCR_EL2 at vcpu_load() In-Reply-To: References: <20241209180926.2161373-1-oliver.upton@linux.dev> <20241209180926.2161373-13-oliver.upton@linux.dev> <86ed24rg0h.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mizhang@google.com, coltonlewis@google.com, rananta@google.com, james.clark@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 19 Dec 2024 18:00:24 +0000, Oliver Upton wrote: > > On Wed, Dec 18, 2024 at 06:40:46PM +0000, Marc Zyngier wrote: > > On Mon, 09 Dec 2024 18:09:22 +0000, > > Oliver Upton wrote: > > > @@ -288,6 +270,12 @@ void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu) > > > > > > WARN_ON_ONCE(vcpu->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED); > > > vcpu->arch.debug_owner = VCPU_DEBUG_GUEST_OWNED; > > > + > > > + preempt_disable(); > > > + kvm_arm_setup_mdcr_el2(vcpu); > > > + if (has_vhe()) > > > + write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); > > > + preempt_enable(); > > > > I'm not confident that the preemption_disable() does anything. > > Specially given that it doesn't include setting the ownership as part > > of the critical section. So if that works at it is now, then the > > critical section is pointless. > > We use percpu data to construct mdcr_el2, so disabling preemption > ensures that we use the right copy + stick mdcr in the right CPU. Ah crap, I missed the copy of PMCR_EL0.N. Fair enough then. > > But point taken about guest ownership, nothing stops preemption from > blowing away the GUEST_OWNED state. > > > I also find it rather fragile that we have multiple places where we > > write MDCR_EL2, and I would love this to go for good. Any idea? > > Totally agree, that was at least one of the motivators for this series > originally. For v4 I'm planning to hoist the preempt_disable() + programming > of MDCR_EL2 into kvm_arm_setup_mdcr_el2(), which would be shared w/ > vcpu_load() and hide the details of how MDCR gets set up. Yeah, something like that is probably OK, at least for now. > I still want us to have a way of reconfiguring MDCR_EL2 on the fly to > lazily restore the debug registers without going through an entire > put/load. I'm thinking that eventually we can do the same thing for the > PMU when Colton + co have partitioned PMU support worked out. A full load/put is overkill indeed. But something more lightweight and limited to the debug stuff may be useful. That may cause some restructuring, but probably worth it. Thanks, M. -- Without deviation from the norm, progress is not possible.