From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 023B01DDC34 for ; Fri, 28 Feb 2025 09:43:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740735804; cv=none; b=dVHBjWGnUTYqawlZO86SnibPRFWKhujC/RVZ4+n+AqEtN06pCjpvbbsE8QzT+L6nq8Os7FiphBKtTJ9FlmIhTpHEu/SAl0Gwwh52Y1ZMrAftT8TLF8TI00tnbB9eMXWRizq2+ISiLSEOiAfWqkbAuOsjZrEjZezgIHBpADWEzwU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740735804; c=relaxed/simple; bh=ErHeCAesNnkGkf3M+l0YV7DvH8pH/Z9IvRTC76nouv0=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=TTd1JBcIOw9F0OI7XNOGjosJCijf51DFjrCWXYOhfWu+DJyn19jdFmJGdrThTyEQFRMQS/LYdRk/G/22U3UUc9mDu64A6diVT3rS8E/SiJ6zFvQH6iBIMSiPzJVVQb5U7vw9/GnV7HpOdQILRODmSwbeNOugsc6mHkuIfhz+Bf8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nrjvUM2W; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nrjvUM2W" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 631F7C4CED6; Fri, 28 Feb 2025 09:43:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740735803; bh=ErHeCAesNnkGkf3M+l0YV7DvH8pH/Z9IvRTC76nouv0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=nrjvUM2Wa29B3zu0RztRTMGDl4G/k2Er92oPCrTwozCkMA+YIIjj5EyYCTkzcY5c+ zrIR3HBYNV31OUOpbTMoVKFZfw2MZcLZmdxM6vMPgL9q2Mxqj9yhm29c6CWRnn3t9P OcrDLPaxYt/vWCvEN6ngnuFPqtftvDsTvcjW2Hswj1x+U8vTTdsPPivW7Wpc+9NvHc 9hnTyLv7YbzZ8Vrt5wfutlrKJKSI3f+yXMDVBsZtZM0z+kwg6mvr1oM9k/9kwK75Ig vXidRsR/HgAT16+Vm04kU+bjhudTrhejfP43ytrcg4TTzMKXvK5cbUlqw6/r8QQmqB 35ltPokqEOdhg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tnwtt-008zNL-77; Fri, 28 Feb 2025 09:43:21 +0000 Date: Fri, 28 Feb 2025 09:43:20 +0000 Message-ID: <86y0xqpfpj.wl-maz@kernel.org> From: Marc Zyngier To: Leo Yan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, ahmed.genidi@arm.com, ben.horgan@arm.com, catalin.marinas@arm.com, kvmarm@lists.linux.dev, oliver.upton@linux.dev, will@kernel.org Subject: Re: [PATCH 1/2] KVM: arm64: Initialize HCR_EL2.E2H early In-Reply-To: <20250228092955.GC2157064@e132581.arm.com> References: <20250227180526.1204723-1-mark.rutland@arm.com> <20250227180526.1204723-2-mark.rutland@arm.com> <20250228092955.GC2157064@e132581.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: leo.yan@arm.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, ahmed.genidi@arm.com, ben.horgan@arm.com, catalin.marinas@arm.com, kvmarm@lists.linux.dev, oliver.upton@linux.dev, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 28 Feb 2025 09:29:55 +0000, Leo Yan wrote: > > Hi Mark, > > On Thu, Feb 27, 2025 at 06:05:25PM +0000, Mark Rutland wrote: > > [...] > > > +.macro init_el2_hcr val > > + mov_q x0, \val > > + > > + /* > > + * Compliant CPUs advertise their VHE-onlyness with > > + * ID_AA64MMFR4_EL1.E2H0 < 0. On such CPUs HCR_EL2.E2H is RES1, but it > > + * can reset into an UNKNOWN state and might not read as 1 until it has > > + * been initialized explicitly. > > For ID_AA64MMFR4_EL1.E2H0 < 0 case, the code actually clears the > HCR_EL2.E2H bit. > > Hence, the comment should be corrected as: "... it can reset into an > UNKNOWN state and might not read as 0 until it has been initialized > explicitly". The comment is just fine. It is the code that is wrong, as it avoids setting E2H when E2H0 < 0 while we want the exact opposite behaviour. As a result, 'b.lt' really should be a 'b.ge'. Or the original code kept as is. > > > + * > > + * Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but > > + * don't advertise it (they predate this relaxation). > > + * > > + * Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H > > + * indicating whether the CPU is running in E2H mode. > > + */ > > I think it is even better to clear the HCR_E2H bit first. This can > avoid any dependency on the passed parameter 'val'. What are you trying to avoid? A random value passed as a parameter to the macro? M. -- Without deviation from the norm, progress is not possible.