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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1go5G6-0001CS-9l; Mon, 28 Jan 2019 11:39:22 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1go5G2-0001C9-N4 for linux-arm-kernel@lists.infradead.org; Mon, 28 Jan 2019 11:39:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24AE0EBD; Mon, 28 Jan 2019 03:39:18 -0800 (PST) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.39.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 06CCC3F59C; Mon, 28 Jan 2019 03:39:14 -0800 (PST) Date: Mon, 28 Jan 2019 11:39:16 +0000 Message-ID: <86y375ui3f.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Julien Thierry Subject: Re: [PATCH v9 19/26] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs In-Reply-To: <1548084825-8803-20-git-send-email-julien.thierry@arm.com> References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-20-git-send-email-julien.thierry@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190128_033918_765307_B75BD0DE X-CRM114-Status: GOOD ( 29.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Jason Cooper , Jonathan Corbet , catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, joel@joelfernandes.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 21 Jan 2019 15:33:38 +0000, Julien Thierry wrote: > > The values non secure EL1 needs to use for PMR and RPR registers depends on > the value of SCR_EL3.FIQ. > > The values non secure EL1 sees from the distributor and redistributor > depend on whether security is enabled for the GIC or not. > > To avoid having to deal with two sets of values for PMR > masking/unmasking, only enable pseudo-NMIs when GIC has non-secure view > of priorities. > > Also, add firmware requirements related to SCR_EL3. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Jonathan Corbet > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Marc Zyngier > --- > Documentation/arm64/booting.txt | 5 ++++ > drivers/irqchip/irq-gic-v3.c | 58 ++++++++++++++++++++++++++++++++++++----- > 2 files changed, 57 insertions(+), 6 deletions(-) > > diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt > index 8df9f46..fbab7e2 100644 > --- a/Documentation/arm64/booting.txt > +++ b/Documentation/arm64/booting.txt > @@ -188,6 +188,11 @@ Before jumping into the kernel, the following conditions must be met: > the kernel image will be entered must be initialised by software at a > higher exception level to prevent execution in an UNKNOWN state. > > + - SCR_EL3.FIQ must have the same value across all CPUs the kernel is > + executing on. > + - The value of SCR_EL3.FIQ must be the same as the one present at boot > + time whenever the kernel is executing. > + > For systems with a GICv3 interrupt controller to be used in v3 mode: > - If EL3 is present: > ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 5a703ae..5374b43 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -66,6 +66,31 @@ struct gic_chip_data { > static struct gic_chip_data gic_data __read_mostly; > static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); > > +/* > + * The behaviours of RPR and PMR registers differ depending on the value of > + * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the > + * distributor and redistributors depends on whether security is enabled in the > + * GIC. > + * > + * When security is enabled, non-secure priority values from the (re)distributor > + * are presented to the GIC CPUIF as follow: > + * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; > + * > + * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure > + * EL1 are subject to a similar operation thus matching the priorities presented > + * from the (re)distributor when security is enabled. > + * > + * see GICv3/GICv4 Architecture Specification (IHI0069D): > + * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt > + * priorities. > + * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 > + * interrupt. > + * > + * For now, we only support pseudo-NMIs if we have non-secure view of > + * priorities. > + */ > +static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); > + > static struct gic_kvm_info gic_v3_kvm_info; > static DEFINE_PER_CPU(bool, has_rss); > > @@ -232,6 +257,12 @@ static void gic_unmask_irq(struct irq_data *d) > gic_poke_irq(d, GICD_ISENABLER); > } > > +static inline bool gic_supports_nmi(void) > +{ > + return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && > + static_branch_likely(&supports_pseudo_nmis); > +} > + > static int gic_irq_set_irqchip_state(struct irq_data *d, > enum irqchip_irq_state which, bool val) > { > @@ -573,6 +604,12 @@ static void gic_update_vlpi_properties(void) > !gic_data.rdists.has_direct_lpi ? "no " : ""); > } > > +/* Check whether it's single security state view */ > +static inline bool gic_dist_security_disabled(void) > +{ > + return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; > +} > + > static void gic_cpu_sys_reg_init(void) > { > int i, cpu = smp_processor_id(); > @@ -598,6 +635,9 @@ static void gic_cpu_sys_reg_init(void) > /* Set priority mask register */ > if (!gic_prio_masking_enabled()) > write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); > + else if (gic_supports_nmi() && group0) > + /* Mismatch configuration with boot CPU */ > + WARN_ON(!gic_dist_security_disabled()); You can probably write this as a single line: WARN_ON(gic_supports_nmi() && group0 && !gic_dist_security_disabled()); Maybe even add a comment saying that in this case, the system is likely to be dead, as the masking of interrupt will not work correctly. > > /* > * Some firmwares hand over to the kernel with the BPR changed from > @@ -852,12 +892,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, > #endif > > #ifdef CONFIG_CPU_PM > -/* Check whether it's single security state view */ > -static bool gic_dist_security_disabled(void) > -{ > - return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; > -} > - > static int gic_cpu_pm_notifier(struct notifier_block *self, > unsigned long cmd, void *v) > { > @@ -1110,6 +1144,11 @@ static bool gic_enable_quirk_msm8996(void *data) > return true; > } > > +static void gic_enable_nmi_support(void) > +{ > + static_branch_enable(&supports_pseudo_nmis); > +} > + > static int __init gic_init_bases(void __iomem *dist_base, > struct redist_region *rdist_regs, > u32 nr_redist_regions, > @@ -1179,6 +1218,13 @@ static int __init gic_init_bases(void __iomem *dist_base, > its_cpu_init(); > } > > + if (gic_prio_masking_enabled()) { > + if (!gic_has_group0() || gic_dist_security_disabled()) > + gic_enable_nmi_support(); > + else > + pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); > + } > + > return 0; > > out_free: > -- > 1.9.1 > Otherwise: Acked-by: Marc Zyngier M. -- Jazz is not dead, it just smell funny. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41229C282C8 for ; Mon, 28 Jan 2019 11:39:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0F1482148E for ; Mon, 28 Jan 2019 11:39:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbfA1LjT (ORCPT ); Mon, 28 Jan 2019 06:39:19 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:43858 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726415AbfA1LjT (ORCPT ); Mon, 28 Jan 2019 06:39:19 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24AE0EBD; Mon, 28 Jan 2019 03:39:18 -0800 (PST) Received: from big-swifty.misterjones.org (big-swifty.cambridge.arm.com [10.1.39.122]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 06CCC3F59C; Mon, 28 Jan 2019 03:39:14 -0800 (PST) Date: Mon, 28 Jan 2019 11:39:16 +0000 Message-ID: <86y375ui3f.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Julien Thierry Cc: , , , , , , , , , Jonathan Corbet , Thomas Gleixner , Jason Cooper Subject: Re: [PATCH v9 19/26] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs In-Reply-To: <1548084825-8803-20-git-send-email-julien.thierry@arm.com> References: <1548084825-8803-1-git-send-email-julien.thierry@arm.com> <1548084825-8803-20-git-send-email-julien.thierry@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Jan 2019 15:33:38 +0000, Julien Thierry wrote: > > The values non secure EL1 needs to use for PMR and RPR registers depends on > the value of SCR_EL3.FIQ. > > The values non secure EL1 sees from the distributor and redistributor > depend on whether security is enabled for the GIC or not. > > To avoid having to deal with two sets of values for PMR > masking/unmasking, only enable pseudo-NMIs when GIC has non-secure view > of priorities. > > Also, add firmware requirements related to SCR_EL3. > > Signed-off-by: Julien Thierry > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Jonathan Corbet > Cc: Thomas Gleixner > Cc: Jason Cooper > Cc: Marc Zyngier > --- > Documentation/arm64/booting.txt | 5 ++++ > drivers/irqchip/irq-gic-v3.c | 58 ++++++++++++++++++++++++++++++++++++----- > 2 files changed, 57 insertions(+), 6 deletions(-) > > diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt > index 8df9f46..fbab7e2 100644 > --- a/Documentation/arm64/booting.txt > +++ b/Documentation/arm64/booting.txt > @@ -188,6 +188,11 @@ Before jumping into the kernel, the following conditions must be met: > the kernel image will be entered must be initialised by software at a > higher exception level to prevent execution in an UNKNOWN state. > > + - SCR_EL3.FIQ must have the same value across all CPUs the kernel is > + executing on. > + - The value of SCR_EL3.FIQ must be the same as the one present at boot > + time whenever the kernel is executing. > + > For systems with a GICv3 interrupt controller to be used in v3 mode: > - If EL3 is present: > ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 5a703ae..5374b43 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -66,6 +66,31 @@ struct gic_chip_data { > static struct gic_chip_data gic_data __read_mostly; > static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); > > +/* > + * The behaviours of RPR and PMR registers differ depending on the value of > + * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the > + * distributor and redistributors depends on whether security is enabled in the > + * GIC. > + * > + * When security is enabled, non-secure priority values from the (re)distributor > + * are presented to the GIC CPUIF as follow: > + * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80; > + * > + * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure > + * EL1 are subject to a similar operation thus matching the priorities presented > + * from the (re)distributor when security is enabled. > + * > + * see GICv3/GICv4 Architecture Specification (IHI0069D): > + * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt > + * priorities. > + * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 > + * interrupt. > + * > + * For now, we only support pseudo-NMIs if we have non-secure view of > + * priorities. > + */ > +static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); > + > static struct gic_kvm_info gic_v3_kvm_info; > static DEFINE_PER_CPU(bool, has_rss); > > @@ -232,6 +257,12 @@ static void gic_unmask_irq(struct irq_data *d) > gic_poke_irq(d, GICD_ISENABLER); > } > > +static inline bool gic_supports_nmi(void) > +{ > + return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && > + static_branch_likely(&supports_pseudo_nmis); > +} > + > static int gic_irq_set_irqchip_state(struct irq_data *d, > enum irqchip_irq_state which, bool val) > { > @@ -573,6 +604,12 @@ static void gic_update_vlpi_properties(void) > !gic_data.rdists.has_direct_lpi ? "no " : ""); > } > > +/* Check whether it's single security state view */ > +static inline bool gic_dist_security_disabled(void) > +{ > + return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; > +} > + > static void gic_cpu_sys_reg_init(void) > { > int i, cpu = smp_processor_id(); > @@ -598,6 +635,9 @@ static void gic_cpu_sys_reg_init(void) > /* Set priority mask register */ > if (!gic_prio_masking_enabled()) > write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1); > + else if (gic_supports_nmi() && group0) > + /* Mismatch configuration with boot CPU */ > + WARN_ON(!gic_dist_security_disabled()); You can probably write this as a single line: WARN_ON(gic_supports_nmi() && group0 && !gic_dist_security_disabled()); Maybe even add a comment saying that in this case, the system is likely to be dead, as the masking of interrupt will not work correctly. > > /* > * Some firmwares hand over to the kernel with the BPR changed from > @@ -852,12 +892,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, > #endif > > #ifdef CONFIG_CPU_PM > -/* Check whether it's single security state view */ > -static bool gic_dist_security_disabled(void) > -{ > - return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; > -} > - > static int gic_cpu_pm_notifier(struct notifier_block *self, > unsigned long cmd, void *v) > { > @@ -1110,6 +1144,11 @@ static bool gic_enable_quirk_msm8996(void *data) > return true; > } > > +static void gic_enable_nmi_support(void) > +{ > + static_branch_enable(&supports_pseudo_nmis); > +} > + > static int __init gic_init_bases(void __iomem *dist_base, > struct redist_region *rdist_regs, > u32 nr_redist_regions, > @@ -1179,6 +1218,13 @@ static int __init gic_init_bases(void __iomem *dist_base, > its_cpu_init(); > } > > + if (gic_prio_masking_enabled()) { > + if (!gic_has_group0() || gic_dist_security_disabled()) > + gic_enable_nmi_support(); > + else > + pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n"); > + } > + > return 0; > > out_free: > -- > 1.9.1 > Otherwise: Acked-by: Marc Zyngier M. -- Jazz is not dead, it just smell funny.