From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: [PATCH 06/43] drm/i915: protect force_wake_(get|put) with the gt_lock Date: Tue, 03 Jan 2012 10:51:25 -0800 Message-ID: <86zke4mxg2.fsf@sumi.keithp.com> References: <1323867460-5486-1-git-send-email-daniel.vetter@ffwll.ch> <1323867460-5486-6-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1778496006==" Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 3917F9FD6D for ; Tue, 3 Jan 2012 10:49:50 -0800 (PST) In-Reply-To: <1323867460-5486-6-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Cc: Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org --===============1778496006== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Wed, 14 Dec 2011 13:57:03 +0100, Daniel Vetter = wrote: > The problem this patch solves is that the forcewake accounting > necessary for register reads is protected by dev->struct_mutex. But the > hangcheck and error_capture code need to access registers without > grabbing this mutex because we hold it while waiting for the gpu. > So a new lock is required. Because currently the error_state capture > is called from the error irq handler and the hangcheck code runs from > a timer, it needs to be an irqsafe spinlock (note that the registers > used by the irq handler (neglecting the error handling part) only uses > registers that don't need the forcewake dance). I think this description is wrong -- the only difference between using atomic objects and using a spinlock is that with the spinlock the call to ->force_wake_get is correctly serialized so that no register access can occur without the chip being awoken. Without a spinlock, a second thread can pass right through gen6_gt_force_wake_get and then go touch registers while the first thread is busy waking the chip up. =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUBTwNOLTYtFsjWk68qAQgAxg//XG2DCKTeYoW8g7xEQcb889N7BDzfbqfL YUF/WQvnQY2zJj33npgmIW0nTspVrEOufKiWREYf0OEer8tijvHdZ20UV85cOlMv hcyIaKLQDcel5PEjNTy2PLTSQTskcIOTT2stmUt5J3aFNsNkh6X4GcIUd9yzGMKy 7/JaArfZIec54X0gQaZWLg3BMkfwJOFPBumZs2V2RRtX9GvDP16JHDNOo1OCgFLg CHA3/mSOsU9iEeIWmBpWmh2qqSlkP7lZc64I0u3A/D8efQV90v7n2EhZ5lTBMO1j /NfoKHzxs3fzLhhDb+ZdkZn+rNpK1RjZG0wEcnvhYoCUX+hYF6LoXsA3QWSrCIQx et1OUj4clFNGWU8sZRoDc6VfGYd+7ZWHcwjpGFdMRq+Cl3WJ3jZFZEPvPYg54mZ6 75tgxT7B+3xKdRT8O2hRJX0fHwO/aVNi8dEbNDLQni8CDAf2IllF8oTCRwEbUtvV FxOdOJvm9tAq/x9WAkp9IUTo+8Mvf4Tkv5I8RKxP+KueQvTE2sgAox/hl5goFGG9 xXGkZTn3TD8LK2ap7UulhxSL3kWdxVHzpkmbo4gQttjKoqlqbFzI2HCQBf3PgEvT Ep2KqO1vmitpqhpB+Zk1ij0bfucDnSwm6GkEsNNcDRW+9usVQ9R72yoUMa3LSHlG R6HmsHOTusQ= =BPCs -----END PGP SIGNATURE----- --=-=-=-- --===============1778496006== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============1778496006==--